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Datasheet, Volume 2 23

Processor Configuration Registers

2.3.2.6 GFX Stolen Spaces

2.3.2.6.1 GTT Stolen Space (GSM)

GSM is allocated to store the GFX translation table entries.

GSM always exists regardless of VT-d as long as internal GFX is enabled. This space is

allocated to store accesses as page table entries are getting updated through virtual

GTTMMADR range. Hardware is responsible to map PTEs into this physical space.

Direct accesses to GSM are not allowed, only hardware translations and fetches can be

directed to GSM.

2.3.2.7 ME UMA

ME (the iAMT Manageability Engine) can be allocated UMA memory. ME memory is

“stolen” from the top of the Host address map. The ME stolen memory base is

calculated by subtracting the amount of memory stolen by the Manageability Engine

from TOM.

Only ME can access this space; it is not accessible by or coherent with any processor

side accesses.

2.3.3 PCI Memory Address Range (TOLUD – 4 GB)

This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally

mapped to the DMI Interface.

Device 0 exceptions are:

1. Addresses decoded to the egress port registers (PXPEPBAR)

2. Addresses decoded to the memory mapped range for internal MCH registers

(MCHBAR)

3. Addresses decoded to the registers associated with the MCH/ICH Serial

Interconnect (DMI) register memory range. (DMIBAR)

For each PCI Express port, there are two exceptions to this rule:

1. Addresses decoded to the PCI Express Memory Window defined by the MBASE,

MLIMIT, registers are mapped to PCI Express.

2. Addresses decoded to the PCI Express prefetchable Memory Window defined by the

PMBASE, PMLIMIT, registers are mapped to PCI Express.

In integrated graphics configurations, there are exceptions to this rule:

1. Addresses decode to the internal graphics translation window (GMADR)

2. Addresses decode to the Internal graphics translation table or IGD registers.

(GTTMMADR)

In a VT enable configuration, there are exceptions to this rule:

1. Addresses decoded to the memory mapped window to PEG/DMI VC0 VT remap

engine registers (VTDPVC0BAR)

2. Addresses decoded to the memory mapped window to Graphics VT remap engine

registers (GFXVTBAR)

3. TCm accesses (to ME stolen memory) from PCH do not go through VT remap

engines.

Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.

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Intel E3-1275 Fiche technique Page 23

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