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Datasheet, Volume 2 211
Processor Configuration Registers
2.13.8 TC_RFP_C0—Refresh Parameters Register
2.13.9 TC_RFTP_C0—Refresh Timing Parameters Register
B/D/F/Type: 0/0/0/MCHBAR MC0
Address Offset: 4294-4297h
Default Value: 0000_980Fh
Access: RW-L
Size: 32 bits
BIOS Optimal Default: 0000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:18 RO 0h Reserved
17:16 RW-L 00b Uncore
Double Refresh Control (DOUBLE_REFRESH_CONTROL)
This field will allow the double self refresh enable/disable.
00b = Double refresh rate when DRAM is WARM/HOT.
01b = Force double self refresh regardless of temperature.
10b = Disable double self refresh regardless of temperature.
11b = Reserved
15:12 RW-L 9h Uncore
Refresh panic WM (Refresh_panic_wm)
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to
use the maximum no-refresh period possible.
11:8 RW-L 8h Uncore
Refresh high priority WM (Refresh_HP_WM)
tREFI count level that turns the refresh priority to high (default is
8)
7:0 RW-L 0Fh Uncore
Rank idle timer for opportunistic refresh (OREF_RI)
Rank idle period that defines an opportunity for refresh, in DCLK
cycles.
B/D/F/Type: 0/0/0/MCHBAR MC0
Address Offset: 4298-429Bh
Default Value: 46B4_1004h
Access: RW-L
Size: 32 bits
Bit Attr
Reset
Value
RST/
PWR
Description
31:25 RW-L 23h Uncore
9 * tREFI (tREFIx9)
Period of minimum between 9*tREFI and tRAS maximum (normally
70 us) in 1024 * DCLK cycles (default is 35) – need to reduce 100
DCLK cycles – uncertainty on timing of panic refresh.
24:16 RW-L 0B4h Uncore
Refresh execution time (tRFC)
Time of refresh – from beginning of refresh until next ACT or
refresh is allowed (in DCLK cycles; default is 180).
15:0 RW-L 1004h Uncore
tREFI period in DCLK cycles (tREFI)
Defines the average period between refreshes, and the rate that
tREFI counter is incremented (in DCLK cycles; default is 4100).
- Processor E3-1200 Family 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- Revision History 10
- 1 Introduction 11
- Introduction 12
- 2 Processor Configuration 13
- 2.3 System Address Map 15
- 16 Datasheet, Volume 2 16
- HOST/SYSTEM VIEW 17
- PHYSICAL MEMORY 17
- (DRAM CONTROLLER VIEW) 17
- 2.3.1 Legacy Address Range 18
- Datasheet, Volume 2 19 19
- 2.3.2.2 TSEG 21
- 2.3.2.5 Pre-allocated Memory 22
- 2.3.2.6 GFX Stolen Spaces 23
- 2.3.2.7 ME UMA 23
- 24 Datasheet, Volume 2 24
- 2.3.3.4 High BIOS Area 25
- 26 Datasheet, Volume 2 26
- Datasheet, Volume 2 27 27
- 2.3.4.3 Memory Remapping 28
- 2.3.4.5 Programming Model 28
- Datasheet, Volume 2 31 31
- 32 Datasheet, Volume 2 32
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.3.11 I/O Address Space 36
- 2.3.12 MCTP and KVM Flows 37
- 38 Datasheet, Volume 2 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 44 Datasheet, Volume 2 44
- Datasheet, Volume 2 45 45
- 2.4.1 I/O Mapped Registers 46
- CAPPTR contains an 51
- 8h in the standard PCI 52
- 2.5.6 CC—Class Code Register 53
- 2.5.30 G Memory Base Register 78
- 2.5.34 SMI Command Register 81
- 22–23 for channel 1) 83
- 2.6.6 CC1—Class Code Register 92
- Register 101
- Port Command Register 113
- Configuration Registers 127
- 108–10Bh 128
- 10C–10Dh 128
- 110–113h 129
- 114–117h 130
- 11A–11Bh 131
- 208–20Bhh 131
- 2.8.6 CC—Class Code Register 136
- Mapped Range Address Register 138
- for details 139
- Device uses INTA# 141
- 2.9 Device 2 I/O Registers 144
- PCI device 147
- -Posted 149
- 2 RW 0b Uncore 163
- 104–107h 183
- 2.12 DMIBAR Registers 188
- Declaration Capability 198
- BC0–BC3h 206
- BCC–BCGh 206
- Channel 0 207
- 40C8–40CBh 210
- 40CC–40CFh 210
- 4294-4297h 211
- 4298-429Bh 211
- Channel 1 212
- 44C8–44CBh 215
- 44CC–44CFh 215
- 4694–4697h 216
- 4698–469Bh 216
- Register Symbol Register Name 217
- 740C–740Fh 217
- 5004–5007h 219
- 5008–500Bh 220
- 5060–5063h 221
- 4CB0-4CB3h 222
- 4CC8–4CCBh 223
- 4CCC–4CCFh 223
- Registers 225
- 100–107h 254
- 108–10Fh 255
- 200–207h 257
- 208–20Fh 258
- FF0–FF3h 259
- 2.19 PCU MCHBAR Registers 260
- 5880–5883h 261
- 5888–588Bh 262
- Report Register 263
- Temperature Report Register 264
- 5948-594Bh 265
- 5998-599Bh 265
- 5D10–5D17h 266
- 2.20 PXPEPBAR Registers 268
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