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Processor Configuration Registers

210 Datasheet, Volume 2

2.13.6 ECCERRLOG0_C0—ECC Error Log 0 Register

2.13.7 ECCERRLOG1_C0—ECC Error Log 1 Register

B/D/F/Type: 0/0/0/MCHBAR MC0

Address Offset: 40C8–40CBh

Reset Value: 0000_0000h

Access: ROS-V

Size: 32 bits

BIOS Optimal Default 0000h

Bit Attr

Reset

Value

RST/

PWR

Description

31:29 ROS-V 000b

Powerg

ood

Error Bank (ERRBANK)

This field holds the Bank Address of the read transaction that had

the ECC error.

28:27 ROS-V 00b

Powerg

ood

Error Rank (ERRRANK)

This field holds the Rank ID of the read transaction that had the

ECC error.

26:24 ROS-V 000b

Powerg

ood

Error Chunk (ERRCHUNK)

Holds the chunk number of the error stored in the register.

23:16 ROS-V 00h

Powerg

ood

Error Syndrome (ERRSYND)

This field contains the error syndrome. A value of FFh indicates

that the error is due to poisoning.

15:2 RO 0h Reserved

1 ROS-V 0b

Powerg

ood

Uncorrectable Error Status (MERRSTS)

This bit is set when an uncorrectable multiple-bit error occurs on a

memory read data transfer. When this bit is set, the address that

caused the error and the error syndrome are also logged and they

are locked until this bit is cleared.

This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS

is cleared.

0 ROS-V 0b

Powerg

ood

Correctable Error Status (CERRSTS)

This bit is set when a correctable single-bit error occurs on a

memory read data transfer. When this bit is set, the address that

caused the error and the error syndrome are also logged and they

are locked to further single bit errors, until this bit is cleared.

A multiple bit error that occurs after this bit is set will override the

address/error syndrome information.

This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS

is cleared.

B/D/F/Type: 0/0/0/MCHBAR MC0

Address Offset: 40CC–40CFh

Reset Value: 0000_0000h

Access: ROS-V

Size: 32 bits

Bit Attr

Reset

Value

RST/

PWR

Description

31:16 ROS-V 0000h

Powerg

ood

Error Column (ERRCOL)

This field holds the DRAM column address of the read transaction

that had the ECC error.

15:0 ROS-V 0000h

Powerg

ood

Error Row (ERRROW)

This field holds the DRAM row (page) address of the read

transaction that had the ECC error.

1 2 ... 205 206 207 208 209 210 211 212 213 214 215 ... 299 300

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Intel E3-1275 Fiche technique Page 210

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