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Datasheet, Volume 2 239
Processor Configuration Registers
2.18.8 FSTS_REG—Fault Status Register
This register indicates the various error status.
B/D/F/Type: 0/0/0/GFXVTBAR
Address Offset: 34–37h
Reset Value: 0000_0000h
Access: RO, ROS-V, RW1CS
Size: 32 bits
BIOS Optimal Default 00000h
Bit Attr
Reset
Value
RST/
PWR
Description
31:16 RO 0h Reserved
15:8 ROS-V 00h
Powerg
ood
Fault Record Index (FRI)
This field is valid only when the PPF field is set.
The FRI field indicates the index (from base) of the fault recording
register to which the first pending fault was recorded when the PPF
field was Set by hardware.
The value read from this field is undefined when the PPF field is
clear.
7 RO 0h Reserved
6 RO 0b Uncore
Invalidation Time-out Error (ITE)
Hardware detected a Device-IOTLB invalidation completion time-
out. At this time, a fault event may be generated based on the
programming of the Fault Event Control register.
Hardware implementations not supporting device Device-IOTLBs
implement this bit as RsvdZ.
5 RO 0b Uncore
Invalidation Completion Error (ICE)
Hardware received an unexpected or invalid Device-IOTLB
invalidation completion. This could be due to either an invalid ITag
or invalid source-id in an invalidation completion response. At this
time, a fault event may be generated based on the programming of
the Fault Event Control register.
Hardware implementations not supporting Device-IOTLBs
implement this bit as RsvdZ.
4 RW1CS 0b
Powerg
ood
Invalidation Queue Error (IQE)
Hardware detected an error associated with the invalidation queue.
This could be due to either a hardware error while fetching a
descriptor from the invalidation queue, or hardware detecting an
erroneous or invalid descriptor in the invalidation queue. At this
time, a fault event may be generated based on the programming of
the Fault Event Control register.
Hardware implementations not supporting queued invalidations
implement this bit as RsvdZ.
3 RO 0b Uncore
Advanced Pending Fault (APF)
When this bit is 0, hardware sets this bit when the first fault record
(at index 0) is written to a fault log. At this time, a fault event is
generated based on the programming of the Fault Event Control
register.
Software writing 1 to this field clears it. Hardware implementations
not supporting advanced fault logging implement this bit as RsvdZ.
2 RO 0b Uncore
Advanced Fault Overflow (AFO)
Hardware sets this bit to indicate advanced fault log overflow
condition. At this time, a fault event is generated based on the
programming of the Fault Event Control register.
Software writing 1 to this field clears it.
Hardware implementations not supporting advanced fault logging
implement this bit as RsvdZ.
- Processor E3-1200 Family 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- Revision History 10
- 1 Introduction 11
- Introduction 12
- 2 Processor Configuration 13
- 2.3 System Address Map 15
- 16 Datasheet, Volume 2 16
- HOST/SYSTEM VIEW 17
- PHYSICAL MEMORY 17
- (DRAM CONTROLLER VIEW) 17
- 2.3.1 Legacy Address Range 18
- Datasheet, Volume 2 19 19
- 2.3.2.2 TSEG 21
- 2.3.2.5 Pre-allocated Memory 22
- 2.3.2.6 GFX Stolen Spaces 23
- 2.3.2.7 ME UMA 23
- 24 Datasheet, Volume 2 24
- 2.3.3.4 High BIOS Area 25
- 26 Datasheet, Volume 2 26
- Datasheet, Volume 2 27 27
- 2.3.4.3 Memory Remapping 28
- 2.3.4.5 Programming Model 28
- Datasheet, Volume 2 31 31
- 32 Datasheet, Volume 2 32
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.3.11 I/O Address Space 36
- 2.3.12 MCTP and KVM Flows 37
- 38 Datasheet, Volume 2 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 44 Datasheet, Volume 2 44
- Datasheet, Volume 2 45 45
- 2.4.1 I/O Mapped Registers 46
- CAPPTR contains an 51
- 8h in the standard PCI 52
- 2.5.6 CC—Class Code Register 53
- 2.5.30 G Memory Base Register 78
- 2.5.34 SMI Command Register 81
- 22–23 for channel 1) 83
- 2.6.6 CC1—Class Code Register 92
- Register 101
- Port Command Register 113
- Configuration Registers 127
- 108–10Bh 128
- 10C–10Dh 128
- 110–113h 129
- 114–117h 130
- 11A–11Bh 131
- 208–20Bhh 131
- 2.8.6 CC—Class Code Register 136
- Mapped Range Address Register 138
- for details 139
- Device uses INTA# 141
- 2.9 Device 2 I/O Registers 144
- PCI device 147
- -Posted 149
- 2 RW 0b Uncore 163
- 104–107h 183
- 2.12 DMIBAR Registers 188
- Declaration Capability 198
- BC0–BC3h 206
- BCC–BCGh 206
- Channel 0 207
- 40C8–40CBh 210
- 40CC–40CFh 210
- 4294-4297h 211
- 4298-429Bh 211
- Channel 1 212
- 44C8–44CBh 215
- 44CC–44CFh 215
- 4694–4697h 216
- 4698–469Bh 216
- Register Symbol Register Name 217
- 740C–740Fh 217
- 5004–5007h 219
- 5008–500Bh 220
- 5060–5063h 221
- 4CB0-4CB3h 222
- 4CC8–4CCBh 223
- 4CCC–4CCFh 223
- Registers 225
- 100–107h 254
- 108–10Fh 255
- 200–207h 257
- 208–20Fh 258
- FF0–FF3h 259
- 2.19 PCU MCHBAR Registers 260
- 5880–5883h 261
- 5888–588Bh 262
- Report Register 263
- Temperature Report Register 264
- 5948-594Bh 265
- 5998-599Bh 265
- 5D10–5D17h 266
- 2.20 PXPEPBAR Registers 268
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