Intel I5 Manuel d'utilisateur télécharger pdf (Page 9)

Specification Update 9

BU7

XXNo Fix

General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be

Preempted

BU8

XXNo Fix

LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in

64-bit Mode

BU9

XXNo Fix

Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/XRSTOR

Image Leads to Partial Memory Update

BU10

XXNo FixValues for LBR/BTS/BTM Will be Incorrect after an Exit from SMM

BU11

XXNo Fix

EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation

Change

BU12

XXNo FixB0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set

BU13

XXNo FixMCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error

BU14

XXNo FixDebug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints

BU15

XXNo FixLER MSRs May Be Unreliable

BU16

XXNo FixStorage of PEBS Record Delayed Following Execution of MOV SS or STI

BU17

XXNo FixPEBS Record not Updated when in Probe Mode

BU18

XXNo FixMONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang

BU19

XXNo FixFaulting MMX Instruction May Incorrectly Update x87 FPU Tag Word

BU20

XXNo Fix

An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a

System Hang

BU21

XXNo Fix

#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not

Provide Correct Exception Error Code

BU22

XXNo Fix

DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is

Followed by a Store or an MMX Instruction

BU23

XXNo FixAPIC Error “Received Illegal Vector” May be Lost

BU24

XXNo Fix

Changing the Memory Type for an In-Use Page Translation May Lead to Memory-

Ordering Violations

BU25

XXNo Fix

Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data

Structures

BU26

XXNo Fix

LBR, BTM or BTS Records May have Incorrect Branch From Information After an EIST/

T-state/S-state/C1E Transition or Adaptive Thermal Throttling

BU27

XXNo Fix

Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation

Descriptors

BU28

XXNo Fix

FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which

Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode

BU29

XXNo Fix

VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported Field in

VMCS

BU30

XXNo FixSpurious Interrupts May be Generated From the Intel® VT-d Remap Engine

BU31

XXNo Fix

Malformed PCIe Transactions May be Treated as Unsupported Requests Instead of as

Critical Errors

BU32

XXNo Fix

Reception of Certain Malformed Transactions May Cause PCIe Port to Hang Rather

Than Reporting an Error

BU33

XXNo FixClock Modulation Duty Cycle Cannot be Programmed to 6.25%

Errata (Sheet 2 of 5)

Number

Steppings

Status ERRATA

E-1 L-1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 55 56

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Intel I5 Manuel d'utilisateur Page 9

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