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Specification Update 39

BU63. PCIe* Root-port Initiated Compliance State Transmitter Equalization

Settings May be Incorrect

Problem: If the processor is directed to enter PCIe Polling.Compliance at 5.0 GT/s or 8.0 GT/s

transfer rates, it should use the Link Control 2 Compliance Preset/De-emphasis field

(bits [15:12]) to determine the correct de-emphasis level. Due to this erratum, when

the processor is directed to enter Polling.Compliance from 2.5 GT/s transfer rate, it

retains 2.5 GT/s de-emphasis values.

Implication: The processor may operate in Polling.Compliance mode with an incorrect transmitter

de-emphasis level.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BU64. PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s

Problem: Due to this erratum, if a link partner transitions to RxL0s state within 20 ns of entering

L0 state, the PCIe controller may incorrectly log an error in ?Correctable Error

Status.Receiver Error Status? field (Bus 0, Device 2, Function 0, 1, 2 and Device 6,

Function 0, offset 1D0H, bit 0).

Implication: Correctable receiver errors may be incorrectly logged. Intel has not observed any

functional impact due to this erratum with any commercially available add-in cards.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BU65. Reception of Certain Malformed Transactions May Cause PCIe* Port to

Hang Rather Than Reporting an Error

Problem: If the processor receives an upstream malformed non posted packet for which the type

field is IO, Configuration or the deprecated TCfgRd and the format is 4 DW header, then

due to this erratum the integrated PCIe controller may hang instead of reporting the

malformed packet error or issuing an unsupported request completion transaction.

Implication: Due to this erratum, the processor may hang without reporting errors when receiving a

malformed PCIe transaction. Intel has not observed this erratum with any commercially

available device.

Workaround: None identified. Upstream transaction initiators should avoid issuing unsupported

requests with 4 DW header formats.

Status: For the steppings affected, see the Summary Tables of Changes.

BU66. PCIe* Link Width May Degrade After a Warm Reset

Problem: PCIe link width may degrade after a warm reset if the Link is operating at 8.0 GT/s or

5.0 GT/s transfer speeds prior to the reset.

Implication: Due to this erratum, the PCIe link may retain to a narrower width, e.g. from x16 to x4.

Workaround: A BIOS code change has been identified and may be implemented as a workaround for

this erratum. .

Status: For the steppings affected, see the Summary Tables of Changes.

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Intel I5 Manuel d'utilisateur Page 39