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Specification Update 35

BU48. 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI

And RSI Before Any Data is Transferred

Problem: If a REP MOVSB/STOSB is executed in 64-bit mode with an address size of 32 bits, and

if an interrupt is being recognized at the start of the instruction operation, the upper

32-bits of RCX, RDI and RSI may be cleared, even though no data has yet been copied

or written.

Implication: Due to this erratum, the upper 32-bits of RCX, RDI and RSI may be prematurely

cleared.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

BU49. An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB

May Result EFLAGS.RF Being Incorrectly Set

Problem: If a REP MOVSB/STOSB is executed and an interrupt is recognized prior to completion

of the first iteration of the string operation, EFLAGS may be saved with RF=1 even

though no data has been copied or stored. The Software Developer’s Manual states that

RF will be set to 1 for such interrupt conditions only after the first iteration is complete.

Implication: Software may not operate correctly if it relies on the value saved for EFLAGS.RF when

an interrupt is recognized prior to the first iteration of a string instruction. Debug

exceptions due to instruction breakpoints are delivered correctly despite this erratum;

this is because the erratum occurs only after the processor has evaluated instruction-

breakpoint conditions.

Workaround: Software whose correctness depends on value saved for EFLAGS.RF by delivery of the

affected interrupts can disable fast-string operation by clearing Fast-String Enable in bit

0 in the IA32_MISC_ENABLE MSR (1A0H).

Status: For the steppings affected, see the Summary Tables of Changes.

BU50. Accessing Physical Memory Space 0-640K through the Graphics

Aperture May Cause Unpredictable System Behavior

Problem: The physical memory space 0-640K when accessed through the graphics aperture may

result in a failure for writes to complete or reads to return incorrect results.

Implication: A hang or functional failure may occur during graphics operation such as OGL or OCL

conformance tests, 2D/3D games and graphics intensive application.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

BU51. PEBS May Unexpectedly Signal a PMI After The PEBS Buffer is Full

Problem: The Software Developer’s Manual states that no PMI should be generated when PEBS

index reaches PEBS Absolute Maximum. Due to this erratum, a PMI may be generated

even though the PEBS buffer is full.

Implication: PEBS may trigger a PMI even though the PEBS index has reached the PEBS Absolute

Maximum.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

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Intel I5 Manuel d'utilisateur Page 35