Intel LE80535VC600512 Fiche technique télécharger pdf (Page 37)

Mobile Intel

®

Celeron

®

Processor (0.18µ) in BGA2 and Micro-PGA2 Packages

283654-003 Datasheet 37

Figure 11. Test Timings (Boundary Scan)

TCK

TDI, TMS

Input

Signals

TDO

Output

Signals

0.75V

T

v

T

w

T

r

T

s

T

x

T

u

T

y

T

z

D0008-01

NOTES:

T

r

= T43 (All Non-Test Inputs Setup Time)

T

s

= T44 (All Non-Test Inputs Hold Time)

T

u

= T40 (TDO Float Delay)

T

v

= T37 (TDI, TMS Setup Time)

T

w

= T38 (TDI, TMS Hold Time)

T

x

= T39 (TDO Valid Delay)

T

y

= T41 (All Non-Test Outputs Valid Delay)

T

z

= T42 (All Non-Test Outputs Float Delay)

Figure 12. Test Reset Timings

TRST#

0.75V

T

q

D0009-01

NOTE:

T

q

= T36 (TRST# Pulse Width)

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 79 80

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