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Document Number: 324641-0012nd Generation Intel® Core™ Processor Family Desktop Datasheet, Volume 1Supporting Intel® Core™ i7, i5 and i3 Desktop Proce

Introduction10 Datasheet, Volume 1Figure 1-1. 2nd Generation Intel® Core™ Processor Family Desktop PlatformIntel® Flexible Display InterfaceDMI2 x4Di

Processor Pin and Signal Information100 Datasheet, Volume 1VCCIO AF8 PWRVCCIO AG33 PWRVCCIO AJ16 PWRVCCIO AJ17 PWRVCCIO AJ26 PWRVCCIO AJ28 PWRVCCIO AJ

Processor Pin and Signal InformationDatasheet, Volume 1 101VSS A35 GNDVSS AA33 GNDVSS AA34 GNDVSS AA35 GNDVSS AA36 GNDVSS AA37 GNDVSS AA38 GNDVSS AA6

Processor Pin and Signal Information102 Datasheet, Volume 1VSS AM30 GNDVSS AM36 GNDVSS AM37 GNDVSS AM38 GNDVSS AM39 GNDVSS AM4 GNDVSS AM40 GNDVSS AM5

Processor Pin and Signal InformationDatasheet, Volume 1 103VSS AV11 GNDVSS AV14 GNDVSS AV17 GNDVSS AV3 GNDVSS AV35 GNDVSS AV38 GNDVSS AV6 GNDVSS AW10

Processor Pin and Signal Information104 Datasheet, Volume 1VSS G34 GNDVSS G7 GNDVSS G8 GNDVSS H1 GNDVSS H17 GNDVSS H2 GNDVSS H20 GNDVSS H23 GNDVSS H26

Processor Pin and Signal InformationDatasheet, Volume 1 105§ §VSS V5 GNDVSS W6 GNDVSS Y5 GNDVSS Y8 GNDVSS_NCTF A4 GNDVSS_NCTF AV39 GNDVSS_NCTF AY37 GN

Processor Pin and Signal Information106 Datasheet, Volume 1

Datasheet, Volume 1 107DDR Data Swizzling9 DDR Data SwizzlingTo achieve better memory performance and better memory timing, Intel design performed the

DDR Data Swizzling108 Datasheet, Volume 1Table 9-1. DDR Data Swizzling Table – Channel APin Name Pin # MC Pin NameSA_DQ[0] AJ3 DQ01SA_DQ[1] AJ4 DQ02SA

DDR Data SwizzlingDatasheet, Volume 1 109§ §Table 9-2. DDR Data Swizzling Table – Channle BPin Name Pin # MC Pin NameSB_DQ[0] AG7 DQ03SB_DQ[1] AG8 DQ0

Datasheet, Volume 1 11Introduction1.1 Processor Feature Details• Four or two execution cores• A 32-KB instruction and 32-KB data first-level cache (L

DDR Data Swizzling110 Datasheet, Volume 1

Introduction12 Datasheet, Volume 1• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank devices)• Command launch modes of 1n/

Datasheet, Volume 1 13Introduction• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)• Peer segment destination posted

Introduction14 Datasheet, Volume 1• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port DMA, floppy drive, and LPC bus ma

Datasheet, Volume 1 15Introduction1.3 Power Management Support1.3.1 Processor Core• Full support of ACPI C-states as implemented by the following pro

Introduction16 Datasheet, Volume 11.5 Package• The processor socket type is noted as LGA 1155. The package is a 37.5 x 37.5 mm Flip Chip Land Grid Arr

Datasheet, Volume 1 17IntroductionPEGPCI Express* Graphics. External Graphics using PCI Express* Architecture. A high-speed serial interface whose co

Introduction18 Datasheet, Volume 11.7 Related DocumentsRefer to Table 1-2 for additional information. § §Table 1-2. Related Documents Document Documen

Datasheet, Volume 1 19Interfaces2 InterfacesThis chapter describes the interfaces supported by the processor.2.1 System Memory Interface2.1.1 System

2 Datasheet, Volume 1Legal Lines and Discla imersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR I

Interfaces20 Datasheet, Volume 1Notes:1. System memory configurations are based on availability and are subject to change.2. Interface does not suppor

Datasheet, Volume 1 21Interfaces2.1.3 System Memory Organization ModesThe IMC supports two memory organization modes—single-channel and dual-channel.

Interfaces22 Datasheet, Volume 12.1.3.2.1 Dual-Channel Symmetric Mode Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum pe

Datasheet, Volume 1 23Interfaces2.1.5.2 Command OverlapCommand Overlap allows the insertion of the DRAM commands between the Activate, Precharge, and

Interfaces24 Datasheet, Volume 12.2 PCI Express* InterfaceThis section describes the PCI Express interface capabilities of the processor. See the PCI

Datasheet, Volume 1 25Interfacespackets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (f

Interfaces26 Datasheet, Volume 12.2.2 PCI Express* Configuration MechanismThe PCI Express (external graphics) link is mapped through a PCI-to-PCI brid

Datasheet, Volume 1 27Interfaces2.2.4 PCI Express Lanes ConnectionFigure 2-5 demonstrates the PCIe lanes mapping.2.3 Direct Media Interface (DMI)Dire

Interfaces28 Datasheet, Volume 12.3.3 DMI Link DownThe DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link dow

Datasheet, Volume 1 29Interfaces2.4.1 3D and Video Engines for Graphics ProcessingThe 3D graphics pipeline architecture simultaneously operates on di

Datasheet, Volume 1 3Contents1Introduction...

Interfaces30 Datasheet, Volume 12.4.1.2.6 Windower/IZ (WIZ) StageThe WIZ unit performs an early depth test, which removes failing pixels and eliminate

Datasheet, Volume 1 31Interfaces2.4.2 Processor Graphics DisplayThe Processor Graphics controller display pipe can be broken down into three componen

Interfaces32 Datasheet, Volume 12.4.2.1.4 VGAVGA is used for boot, safe mode, legacy games, etc. It can be changed by an application without OS/driver

Datasheet, Volume 1 33Interfaces2.5 Platform Environment Control Interface (PECI)The PECI is a one-wire interface that provides a communication chann

Interfaces34 Datasheet, Volume 1

Datasheet, Volume 1 35Technologies3 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in the processor.The

Technologies36 Datasheet, Volume 13.1.2 Intel® VT-x FeaturesThe processor core supports the following Intel VT-x features:• Extended Page Tables (EPT)

Datasheet, Volume 1 37Technologies3.1.4 Intel® VT-d FeaturesThe processor supports the following Intel VT-d features:• Memory controller and Processo

Technologies38 Datasheet, Volume 13.2 Intel® Trusted Execution Technology (Intel® TXT)Intel Trusted Execution Technology (Intel TXT) defines platform-

Datasheet, Volume 1 39Technologies3.4 Intel® Turbo Boost TechnologyIntel® Turbo Boost Technology is a feature that allows the processor core to oppor

4 Datasheet, Volume 12.4.1.2 3D Pipeline...292.4.1.3 Video Engine ...

Technologies40 Datasheet, Volume 13.5 Intel® Advanced Vector Extensions (AVX)Intel® Advanced Vector Extensions (AVX) is the latest expansion of the In

Datasheet, Volume 1 41Technologies3.7 Intel® 64 Architecture x2APICThe x2APIC architecture extends the xAPIC architecture that provides a key mechani

Technologies42 Datasheet, Volume 1The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the “x2APIC” mode.

Datasheet, Volume 1 43Power Management4 Power ManagementThis chapter provides information on the following power management topics:•ACPI States• Proc

Power Management44 Datasheet, Volume 14.1.3 Integrated Memory Controller States4.1.4 PCIe Link States4.1.5 DMI States 4.1.6 Processor Graphics Control

Datasheet, Volume 1 45Power Management4.1.7 Interface State Combinations4.2 Processor Core Power ManagementWhile executing code, Enhanced Intel Speed

Power Management46 Datasheet, Volume 14.2.2 Low-Power Idle StatesWhen the processor is idle, low-power idle states (C-states) are used to save power.

Datasheet, Volume 1 47Power ManagementNote:1. If enabled, the core C-state will be C1E if all enabled cores have also resolved a core C1 state or hig

Power Management48 Datasheet, Volume 14.2.4 Core C-statesThe following are general rules for all core C-states, unless specified otherwise:• A core C-

Datasheet, Volume 1 49Power ManagementThere are two C-State auto-demotion options:•C6 to C3• C6/C3 To C1The decision to demote a core from C6 to C3 o

Datasheet, Volume 1 54.3.2.1 Initialization Role of CKE... 544.3.2.2 Conditional Self-Refresh

Power Management50 Datasheet, Volume 1Note:1. If enabled, the package C-state will be C1E if all cores have resolved a core C1 state or higher.4.2.5.1

Datasheet, Volume 1 51Power Management4.2.5.2 Package C1/C1ENo additional power reduction actions are taken in the package C1 state. However, if the

Power Management52 Datasheet, Volume 14.3 IMC Power ManagementThe main memory is power managed during normal operation and in low-power ACPI Cx states

Datasheet, Volume 1 53Power ManagementThe processor supports 5 different types of power-down. The different modes are the power-down modes supported

Power Management54 Datasheet, Volume 14.3.2.1 Initialization Role of CKEDuring power-up, CKE is the only input to the SDRAM that has its level recogni

Datasheet, Volume 1 55Power Management4.5 DMI Power Management• Active power management support using L0s/L1 state.4.6 Graphics Power Management4.6.1

Power Management56 Datasheet, Volume 14.6.5 Intel® Graphics Dynamic FrequencyIntel® Graphics Dynamic Frequency Technology is the ability of the proces

Datasheet, Volume 1 57Thermal Management5 Thermal ManagementFor thermal specifications and design guidelines, refer to the 2nd Generation Intel® Core™

Thermal Management58 Datasheet, Volume 1

Datasheet, Volume 1 59Signal Description6 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groups acco

6 Datasheet, Volume 1Figures1-1 2nd Generation Intel® Core™ Processor Family Desktop Platform ...102-1 Intel® Flex Memo

Signal Description60 Datasheet, Volume 16.1 System Memory InterfaceTable 6-2. Memory Channel A Signal Name Description Direction/Buffer TypeSA_BS[2:0]

Datasheet, Volume 1 61Signal Description6.2 Memory Reference and CompensationTable 6-3. Memory Channel B Signal Name Description Direction/Buffer Typ

Signal Description62 Datasheet, Volume 16.3 Reset and Miscellaneous SignalsNotes:1. PCIe bifurcation support varies with the processor and PCH SKUs us

Datasheet, Volume 1 63Signal Description6.4 PCI Express* Based Interface SignalsNotes:1. PE_TX[3:0] and PE_RX[3:0] are only used for platforms that s

Signal Description64 Datasheet, Volume 16.6 DMI6.7 PLL Signals6.8 TAP SignalsTable 6-8. DMI - Processor to PCH Serial Interface Signal Name Descriptio

Datasheet, Volume 1 65Signal Description6.9 Error and Thermal Protection6.10 Power SequencingTable 6-11. Error and Thermal Protection Signal Name Des

Signal Description66 Datasheet, Volume 16.11 Processor Power Signals6.12 Sense Pins6.13 Ground and NCTFTable 6-13. Processor Power Signals Signal Name

Datasheet, Volume 1 67Signal Description6.14 Processor Internal Pull Up/Pull Down§ §Table 6-16. Processor Internal Pull Up/Pull DownSignal Name Pull

Signal Description68 Datasheet, Volume 1

Datasheet, Volume 1 69Electrical Specifications7 Electrical Specifications7.1 Power and Ground LandsThe processor has VCC, VDDQ, VCCPLL, VCCSA, VCCAXG

Datasheet, Volume 1 7Tables1-1 PCIe Supported Configurations in Desktop Products... 121-2 Related Do

Electrical Specifications70 Datasheet, Volume 17.3 Processor Clocking (BCLK[0], BCLK#[0])The processor uses a differential clock to generate the proce

Datasheet, Volume 1 71Electrical SpecificationsTable 7-1. VR 12.0 Voltage Identification Definition (Sheet 1 of 3)VID7VID6VID5VID4VID3VID2VID1VID0HEX

Electrical Specifications72 Datasheet, Volume 10 0 1 0 1 0 1 0 2 A 0.45500 1 0 1 0 1 0 1 0 A A 1.095000 0 1 0 1 0 1 1 2 B 0.46000 1 0 1 0 1 0 1 1 A B

Datasheet, Volume 1 73Electrical Specifications0 1 0 1 0 1 0 1 5 5 0.67000 1 1 0 1 0 1 0 1 D 5 1.310000 1 0 1 0 1 1 0 5 6 0.67500 1 1 0 1 0 1 1 0 D 6

Electrical Specifications74 Datasheet, Volume 17.5 System Agent (SA) VCC VIDThe VCCSA is configured by the processor output pin VCCSA_VID.VCCSA_VID ou

Datasheet, Volume 1 75Electrical Specifications7.7 Signal GroupsSignals are grouped by buffer type and similar characteristics as listed in Table 7 -

Electrical Specifications76 Datasheet, Volume 1Notes:1. Refer to Chapter 6 and Chapter 8 for signal description details.2. SA and SB refer to DDR3 Cha

Datasheet, Volume 1 77Electrical Specifications7.9 Storage Conditions SpecificationsEnvironmental storage condition limits define the temperature and

Electrical Specifications78 Datasheet, Volume 17.10 DC SpecificationsThe processor DC specifications in this section are defined at the processor pads

Datasheet, Volume 1 79Electrical SpecificationsNotes:1. Unless otherwise noted, all specifications in this table are based on estimates and simulation

8 Datasheet, Volume 1Revision History§ §Revision NumberDescriptionRevision Date001 Initial release January 2011

Electrical Specifications80 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table are based on estimates and simulation

Datasheet, Volume 1 81Electrical SpecificationsNotes:1. VCCAXG is VID based rail. 2. Unless otherwise noted, all specifications in this table are base

Electrical Specifications82 Datasheet, Volume 1Notes:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2.

Datasheet, Volume 1 83Electrical SpecificationsNotes:1. Refer to the PCI Express Base Specification for more details.2. VTX-AC-CM-PP and VTX-AC-CM-P a

Electrical Specifications84 Datasheet, Volume 17.11 Platform Environmental Control Interface (PECI) DC SpecificationsPECI is an Intel proprietary inte

Datasheet, Volume 1 85Electrical Specifications7.11.2 DC CharacteristicsThe PECI interface operates at a nominal voltage set by VCCIO. The set of DC e

Electrical Specifications86 Datasheet, Volume 1

Datasheet, Volume 1 87Processor Pin and Signal Information8 Processor Pin and Signal Information8.1 Processor Pin AssignmentsThe processor pinmap quad

Processor Pin and Signal Information88 Datasheet, Volume 1Note: Pin names SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are RSVD on desktop processors. Figure 8-1

Datasheet, Volume 1 89Processor Pin and Signal InformationNote: Pin names SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are RSVD on desktop processors. Figure 8-2

Datasheet, Volume 1 9Introduction1 IntroductionThe 2nd Generation Intel® Core™ processor family desktop is the next generation of 64-bit, multi-core

Processor Pin and Signal Information90 Datasheet, Volume 1Note: Pin names SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are RSVD on desktop processors. Figure 8-3

Datasheet, Volume 1 91Processor Pin and Signal InformationNote: Pin names SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are RSVD on desktop processors. Figure 8-4

Processor Pin and Signal Information92 Datasheet, Volume 1Table 8-1. Processor Pin List by Pin NamePin Name Pin # Buffer Type Dir.BCLK_ITP C40 Diff Cl

Processor Pin and Signal InformationDatasheet, Volume 1 93PE_TX[2] R6 PCI Express OPE_TX[3] U5 PCI Express OPE_TX#[0] P7 PCI Express OPE_TX#[1] T8 PCI

Processor Pin and Signal Information94 Datasheet, Volume 1RSVD AJ30RSVD AJ31RSVD AN20RSVD AP20RSVD AT11RSVD AT14RSVD AU10RSVD AV34RSVD AW34RSVD AY10RS

Processor Pin and Signal InformationDatasheet, Volume 1 95SA_DQ[26] AV9 DDR3 I/OSA_DQ[27] AU9 DDR3 I/OSA_DQ[28] AV7 DDR3 I/OSA_DQ[29] AW7 DDR3 I/OSA_D

Processor Pin and Signal Information96 Datasheet, Volume 1SB_BS[2] AW17 DDR3 OSB_CAS# AK25 DDR3 OSB_CK[0] AL21 DDR3 OSB_CK[1] AL20 DDR3 OSB_CK[2] AL23

Processor Pin and Signal InformationDatasheet, Volume 1 97SB_DQS[6] AL33 DDR3 I/OSB_DQS[7] AG35 DDR3 I/OSB_DQS[8] AN16 DDR3 I/OSB_DQS#[0] AH6 DDR3 I/O

Processor Pin and Signal Information98 Datasheet, Volume 1VCC C36 PWRVCC D13 PWRVCC D14 PWRVCC D15 PWRVCC D16 PWRVCC D18 PWRVCC D19 PWRVCC D21 PWRVCC

Processor Pin and Signal InformationDatasheet, Volume 1 99VCC J28 PWRVCC J30 PWRVCC K15 PWRVCC K16 PWRVCC K18 PWRVCC K19 PWRVCC K21 PWRVCC K22 PWRVCC