Intel I5 Manuel d'utilisateur télécharger pdf (Page 37)

Specification Update 37

BV56. PCI Express* Gen3 Receiver Return Loss May Exceed Specifications

Problem: The PCIe Base Specification includes a graph that sets requirements for maximum

receiver return loss versus frequency. Due to this erratum, the receiver return loss for

common mode and differential mode may exceed those requirements at certain

frequencies. Under laboratory conditions, Intel has observed violations of as much as

dB.

Implication: The PCI Express Gen3 Base Specification for receiver return loss may be exceeded. No

functional failures have been observed due to this erratum.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BV57. Direct Access Via VT-d to The Processor Graphics Device May Lead to a

System Hang

Problem: Under a complex set of conditions, while using VT-d (Virtualization Technology for

Directed I/O) with the processor graphics device, direct access to the virtualized

processor graphics device can lead to a system hang or restart.

Implication: Systems providing direct access to processor graphics device via VT-d may hang or

restart. Intel has not observed this erratum with any commercially available system.

Workaround: VMM’s should ensure that all processor graphics device interactions conform to

guidance published in the Intel® Open Source HD Graphics Programmer's Reference

Manual and driver writers guide.

Status: For the steppings affected, see the Summary Tables of Changes.

BV58. An Event May Intervene Before a System Management Interrupt That

Results from IN or INS

Problem: If an I/O instruction (IN, INS, OUT, or OUTS) results in an SMI (system-management

interrupt), the processor will set the IO_SMI bit at offset 7FA4H in SMRAM. This

interrupt should be delivered immediately after execution of the I/O instruction so that

the software handling the SMI can cause the I/O instruction to be re-executed. Due to

this erratum, it is possible for another event (e.g., a nonmaskable interrupt) to be

delivered before the SMI that follows the execution of an IN or INS instruction.

Implication: If software handling an affected SMI uses I/O instruction restart, the handler for the

intervening event will not be executed.

Workaround: The SMM handler has to evaluate the saved context to determine if the SMI was

triggered by an instruction that read from an I/O port. The SMM handler must not

restart an I/O instruction if the platform has not been configured to generate a

synchronous SMI for the recorded I/O port address.

Status: For the steppings affected, see the Summary Tables of Changes.

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 55 56

Pas de commentaire

Intel I5 Manuel d'utilisateur Page 37