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Specification Update 27

BV21. #GP on Segment Selector Descriptor that Straddles Canonical

Boundary May Not Provide Correct Exception Error Code

Problem: During a #GP (General Protection Exception), the processor pushes an error code on to

the exception handler’s stack. If the segment selector descriptor straddles the

canonical boundary, the error code pushed onto the stack may be incorrect.

Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this

erratum with any commercially available software.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BV22. DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP

SS is Followed by a Store or an MMX Instruction

Problem: Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not

cause a debug exception immediately after MOV/POP SS but will be delayed until the

instruction boundary following the next instruction is reached. After the debug

exception occurs, DR6.B0-B3 bits will contain information about data breakpoints

matched during the MOV/POP SS as well as breakpoints detected by the following

instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about

data breakpoints matched during the MOV/POP SS when the following instruction is

either an MMX instruction that uses a memory addressing mode with an index or a

store instruction.

Implication: When this erratum occurs, DR6 may not contain information about all breakpoints

matched. This erratum will not be observed under the recommended usage of the MOV

SS,r/m or POP SS instructions (i.e., following them only with an instruction that writes

(E/R)SP).

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

BV23. APIC Error “Received Illegal Vector” May be Lost

Problem: APIC (Advanced Programmable Interrupt Controller) may not update the ESR (Error

Status Register) flag Received Illegal Vector bit [6] properly when an illegal vector error

is received on the same internal clock that the ESR is being written (as part of the

write-read ESR access flow). The corresponding error interrupt will also not be

generated for this case.

Implication: Due to this erratum, an incoming illegal vector error may not be logged into ESR

properly and may not generate an error interrupt.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

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Intel I5 Manuel d'utilisateur Page 27