Intel i7-2960XM Fiche technique télécharger pdf (Page 97)

Datasheet 97

2.13.11 MC_DDR_THERM_STATUS0

MC_DDR_THERM_STATUS1

MC_DDR_THERM_STATUS2

This register contains the status portion of the DDR_THERM# functionality as described

in the processor datasheet (i.e., what is happening or has happened with respect to the

pin).

2.14 Integrated Memory Controller Miscellaneous

Registers

2.14.1 MC_DIMM_CLK_RATIO_STATUS

This register contains status information about DIMM clock ratio.

Device: 4, 5, 6

Function: 3

Offset: A4h

Access as a Dword

Bit Type

Reset

Value

Description

2RO0

ASSERTION.

An assertion edge was seen on DDR_THERM#. Write-1-to-clear.

1RO0

DEASSERTION.

A de-assertion edge was seen on DDR_THERM#. Write-1-to-clear.

0RO0

STATE.

Present logical state of DDR_THERM# bit. This is a static indication of the pin,

and may be several clocks out of date due to the delay between the pin and the

signal.

STATE = 0 means DDR_THERM# is deasserted

STATE = 1 means DDR_THERM# is asserted

Device: 3

Function: 4

Offset: 50h

Access as a Dword

Bit Type

Reset

Value

Description

28:24 RO 0

MAX_RATIO. Maximum ratio allowed by the part.

Value = Qclk

00000 = RSVD

00110 = 800 MHz

01000 = 1066 MHz

01010 = 1333 MHz

4:0 RO 0

QCLK_RATIO. Current ratio of Qclk.

Value = Qclk.

00000 = RSVD

00110 = 800 MHz

01000 = 1066 MHz

01010 = 1333 MHz

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