Intel i7-2960XM Fiche technique télécharger pdf (Page 70)

70 Datasheet

2.10.12 MC_CHANNEL_0_BANK_TIMING

MC_CHANNEL_1_BANK_TIMING

MC_CHANNEL_2_BANK_TIMING

This register contains parameters that specify the bank timing parameters. These

values are in DCLK. The values in these registers are encoded where noted. All of these

values apply to commands to the same rank only.

2.10.13 MC_CHANNEL_0_REFRESH_TIMING

MC_CHANNEL_1_REFRESH_TIMING

MC_CHANNEL_2_REFRESH_TIMING

This register contains parameters that specify the refresh timings. Units are in DCLK.

Device: 4, 5, 6

Function: 0

Offset: 88h

Access as a Dword

Bit Type

Reset

Value

Description

21:17 RW 0 tWTPr. Minimum Write CAS to Precharge command delay.

16:13 RW 0 tRTPr. Minimum Read CAS to Precharge command delay.

12:9 RW 0 tRCD. Minimum delay between Activate and CAS commands.

8:4 RW 0 tRAS. Minimum delay between Activate and Precharge commands.

3:0 RW 0 tRP. Minimum delay between Precharge command and Activate command.

Device: 4, 5, 6

Function: 0

Offset: 8Ch

Access as a Dword

Bit Type

Reset

Value

Description

29:19 RW 0

tTHROT_OPPREF.

The minimum time between two opportunistic refreshes. Should be set to tRFC in

DCLKS. Zero is an invalid encoding. A value of 1 should be programmed to disable

the throttling of opportunistic refreshes. By setting this field to tRFC, current to a

single DIMM can be limited to that required to support this scenario without

significant performance impact:

• 8 panic refreshes in tREFI to one rank

• 1 opportunistic refresh every tRFC to another rank

• full bandwidth delivered by the third and fourth ranks

Platforms that can supply peak currents to the DIMMs should disable opportunistic

refresh throttling for max performance.

18:9 RW 0

tREFI_8.

Average periodic refresh interval divided by 8.

8:0 RW 0

tRFC.

Delay between the refresh command and an activate or refresh command.

1 2 ... 65 66 67 68 69 70 71 72 73 74 75 ... 97 98

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MooreCo 27679 manuály

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