Intel BX80623I32100 Fiche technique télécharger pdf (Page 33)

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Datasheet, Volume 1 33

Interfaces

2.5 Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a

PECI client (processor) and a PECI master. The processor implements a PECI interface

to:

• Allow communication of processor thermal and other information to the PECI

master.

• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

2.6 Interface Clocking

2.6.1 Internal Clocking Requirements

§ §

Table 2-4. Reference Clock

Reference Input Clock Input Frequency Associated PLL

BCLK[0]/BCLK#[0] 100 MHz Processor/Memory/Graphics/PCIe/DMI/FDI

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 111 112

Datasheet, Volume 1 1
2 Datasheet, Volume 1 2
Contents 3
4 Datasheet, Volume 1 4
Datasheet, Volume 1 5 5
6 Datasheet, Volume 1 6
Datasheet, Volume 1 7 7
Revision History 8
1 Introduction 9
Introduction 10
1.1 Processor Feature Details 11
1.2 Interfaces 11
1.2.2 PCI Express* 12
Datasheet, Volume 1 13 13
1.2.5 Processor Graphics 14
1.2.6 Intel 14
1.3 Power Management Support 15
1.5 Package 16
1.6 Terminology 16
1.7 Related Documents 18
2 Interfaces 19
Interfaces 20
2.1.3.1 Single-Channel Mode 21
Flex Memory Technology Mode 21
2.1.5.2 Command Overlap 23
2.2 PCI Express* Interface 24
2.2.1.1 Transaction Layer 25
2.2.1.2 Data Link Layer 25
2.2.1.3 Physical Layer 25
2.2.3 PCI Express* Port 26
2.3.1 DMI Error Flow 27
2.3.3 DMI Link Down 28
2.4.1.2 3D Pipeline 29
2.4.1.3 Video Engine 30
2.4.1.4 2D Engine 30
2.4.2.1 Display Planes 31
2.4.3 Intel 32
2.6 Interface Clocking 33
3 Technologies 35
Technologies 36
Datasheet, Volume 1 37 37
3.4 Intel 39
Turbo Boost Technology 39
3.6.1 PCLMULQDQ Instruction 40
Datasheet, Volume 1 41 41
4 Power Management 43
(ACPI) States Supported 44
4.2.1 Enhanced Intel 46
SpeedStep 46
Technology 46
4.2.2 Low-Power Idle States 46
4.2.4 Core C-states 48
4.2.4.2 Core C1/C1E State 49
4.2.4.3 Core C3 State 49
4.2.4.4 Core C6 State 49
4.2.4.5 C-State Auto-Demotion 49
4.2.5 Package C-States 50
4.2.5.1 Package C0 51
4.2.5.2 Package C1/C1E 51
Management 52
Datasheet, Volume 1 53 53
Power Management 53
Datasheet, Volume 1 55 55
4.6 Graphics Power Management 56
4.7 Thermal Power Management 57
5 Thermal Management 59
Thermal Management 60
6 Signal Description 61
Signal Description 62
6.5 Intel 65
6.10 Power Sequencing Signals 67
6.11 Processor Power Signals 68
6.12 Sense Signals 68
7 Electrical Specifications 71
Voltage Identification (VID) 72
Electrical Specifications 74
7.5 System Agent (SA) VCC VID 76
7.7 Signal Groups 77
7.10 DC Specifications 80
(Sheet 2 of 2) 81
Specifications 82
DC Specifications 86
7.11.2 DC Characteristics 87
8 Processor Pin and Signal 89
90 Datasheet, Volume 1 90
Datasheet, Volume 1 91 91
92 Datasheet, Volume 1 92
Datasheet, Volume 1 93 93
108 Datasheet, Volume 1 108
9 DDR Data Swizzling 109
Table – Channel A 110
Table – Channel B 111
DDR Data Swizzling 112

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