Intel BX8060515750 manuels

Intel BX8060515750 Fiche technique (300 pages)

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Table des matières

Core™ i7-800 and i5-700

1

Desktop Processor Series

1

Legal Lines and Disclaimers

2

Contents

3

4 Datasheet, Volume 2

4

Datasheet, Volume 2 5

5

6 Datasheet, Volume 2

6

Datasheet, Volume 2 7

7

8 Datasheet, Volume 2

8

Datasheet, Volume 2 9

9

10 Datasheet, Volume 2

10

Datasheet, Volume 2 11

11

12 Datasheet, Volume 2

12

Datasheet, Volume 2 13

13

14 Datasheet, Volume 2

14

Revision History

15

16 Datasheet, Volume 2

16

1 Introduction

17

Introduction

18

2 Configuration Process and

19

2.2 Configuration Mechanisms

21

22 Datasheet, Volume 2

22

Datasheet, Volume 2 23

23

24 Datasheet, Volume 2

24

Datasheet, Volume 2 25

25

2.5 I/O Mapped Registers

26

Configuration Registers

27

3.2 Device Mapping

28

Extended

29

Configuration Space

29

PCI Device

29

Dependent

29

PCI Header

29

30 Datasheet, Volume 2

30

Express space

36

Integrated I/O bus

38

ID Register

40

“virtual” PCI-to-PCI bridge

46

3.3.3.21 MBAS—Memory Base

47

3.3.3.22 MLIM—Memory Limit

47

Register (Device 0 DMI)

77

23:8 RO 0h Reserved

86

23 RO 0 Reserved

87

Registers (Sheet 1 of 2)

94

Registers (Sheet 2 of 2)

95

(Sheet 2 of 3)

100

“Capabilities List.”

101

(Sheet 2 of 2)

102

3.4.3.1 CAPID—PCI Express

105

Capability List Register

105

3.4.3.3 EXPCAP—PCI Express

106

Capabilities Register

106

3.4.3.2 NXTPTR—PCI Express

106

3.4.3.4 DEVCAP—PCI Express

107

Device Capabilities Register

107

3.4.3.5 DEVCTRL—PCI Express

108

Device Control Register

108

3.4.3.6 DEVSTS—PCI Express

110

Device Status Register

110

3.4.4 Intel

111

Bit Attr Default Description

112

3.4.4.6 NCMEM.BASE—NCMEM Base

113

(Sheet 1 of 3)

114

(Sheet 3 of 3)

116

VT-d Chipset Registers

125

3.4.4.30 VTGENCTRL—Intel

126

3.4.4.33 VTSTS—Intel

128

VT-d Status Register

128

0ACh-0B8h by 4

129

0BCh-0C0h by 4

129

0C4h-0D8h by 4

129

0DCh-0E8h by 4

129

0ECh-0F8h by 4

130

0FCh, 104h -10Ch by 4

130

110h-11Ch by 4

130

18h-124h by 4

131

128h-13Ch by 4

131

140h-14Ch by 4

131

150h-15Ch by 4

132

160h-16Ch by 4

132

170h-17Ch by 4

132

180h-184h by 4

133

188h-19Ch by 4

133

3.4.6.2 GENMCA—Generate MCA

134

3.4.6.3 SYRE—System Reset

135

3.5 Intel

137

VT-d Memory Mapped Registers

137

3.5.1 Intel

138

Table 3-14. Intel

139

3.5.2 Register Description

141

3.5.2.2 VTD_CAP[0:1]—Intel

142

VT-d Capability Register

143

18h, 1018h

144

(Sheet 1 of 2)

145

28h, 1028h

146

34h, 1034h

147

38h, 1038h

148

3Ch, 103Ch

149

40h, 1040h

149

44h, 1044h

149

64h, 1064h

149

68h, 1068h

150

6Ch, 106Ch

150

70h, 1070h

150

78h, 1078h

151

80h, 1080h

151

88h, 1088h

151

Register

152

A0h, 10A0h

153

A4h, 10A4h

153

A8h, 10A8h

153

Event Upper Address Register

154

Table Base Address Register

154

200h, 1200h

155

208h, 1208h

156

3.6 Intel

157

Register Map

157

Table 3-16. Intel

158

Table 3-17. Intel

159

Table 3-18. Intel

160

Table 3-19. Intel

161

3.6.1.1 TXT.STS—Intel

162

XT Status Register

162

Base: TXT_PR Offset: 0000h

163

3.6.1.2 TXT.ESTS—Intel

164

TXT Error Status Register

164

TXT Thread Exists Register

165

TXT Threads Join Register

165

3.6.1.5 TXT.ERRORCODE—Intel

166

TXT Error Code Register

166

3.6.1.6 TXT.CMD.RESET—Intel

166

TXT Close Private Command

167

3.6.1.8 TXT.VER.QPIIF

167

3.6.1.9 TXT.ID—Intel

168

TXT Identifier Register

168

TXT Unlock Base Command

169

TXT SINIT Code Base Register

169

TXT SINIT Memory

170

Size Register

170

3.6.1.14 TXT.MLE.JOIN—Intel

170

TXT MLE Join Base Register

170

3.6.1.15 TXT.HEAP.BASE—Intel

171

TXT HEAP Code Base Register

171

3.6.1.16 TXT.HEAP.SIZE—Intel

171

TXT HEAP Size Register

171

3.6.1.17 TXT.MSEG.BASE—Intel

172

TXT MSEG Base Register

172

3.6.1.18 TXT.MSEG.SIZE—Intel

172

TXT MSEG Size Register

172

TXT Scratch Pad Register 0

173

TXT Scratch Pad Register 1

173

Base: TXT_PR Offset: 0388h

174

TXT Close Locality 2

175

3.6.1.25 TXT.PUBLIC.KEY—Intel

175

TXT Public Key Hash Register

175

3.7 Intel

176

3.7.1 Intel

177

3.7.1.4 QPI[0]LCL—Intel

178

3.7.1.5 QPI[0]LCRDC—Intel

179

3.7.2 Intel

180

Registers

180

3.7.2.1 QPIPCTRL0—Intel

181

3.7.2.2 QPIPISOCRES—Intel

181

Isochronous Reservation

181

3.7.2.3 CAPHDRH—PCI Express

182

4.2 Device Mapping

184

Control Registers

193

Address Registers

194

Rank Registers

195

Thermal Control Registers

196

4.4 PCI Standard Registers

201

202 Datasheet, Volume 2

202

4.4.4 CCR—Class Code Register

204

4.4.7 SID—Subsystem Identity

206

4.4.8 PCICMD—Command Register

207

4.5.1 SAD_PAM0123

209

4.5.2 SAD_PAM456

211

4.5.3 SAD_HEN

212

4.5.4 SAD_SMRAM

212

4.5.5 SAD_PCIEXBAR

213

4.5.6 SAD_TPCIEXBAR

213

4.5.7 SAD_MCSEG_BASE

214

4.5.8 SAD_MCSEG_MASK

214

4.5.9 SAD_MESEG_BASE

215

4.5.10 SAD_MESEG_MASK

215

4.6 Intel

218

4.7.1 MC_CONTROL

220

4.7.3 MC_SMI_CNTRL

221

4.7.4 MC_STATUS

222

4.7.5 MC_RESET_CONTROL

222

4.7.6 MC_CHANNEL_MAPPER

223

4.7.7 MC_MAX_DOD

223

4.7.8 MC_CFG_LOCK

224

4.7.9 MC_RD_CRDT_INIT

225

4.7.10 MC_CRDT_WR_THLD

226

Data Register

230

32 bit Payload

230

Control Register

230

4.9.3 MC_DIMM_CLK_RATIO

232

4.9.4 MC_TEST_LTRCON

232

4.9.5 MC_TEST_PH_CTR

233

4.9.6 MC_TEST_PH_PIS

233

4.9.7 MC_TEST_PAT_GCTR

234

4.9.8 MC_TEST_PAT_BA

235

4.9.9 MC_TEST_PAT_IS

235

4.9.10 MC_TEST_PAT_DCD

235

4.9.11 MC_TEST_EP_SCCTL

236

4.9.12 MC_TEST_EP_SCD

236

MC_CHANNEL_1_DIMM_INIT_CMD

238

MC_CHANNEL_1_DIMM_INIT_PARAMS

239

MC_CHANNEL_1_DIMM_INIT_STATUS

240

4.10.5 MC_CHANNEL_0_DDR3CMD

241

MC_CHANNEL_1_DDR3CMD

241

MC_CHANNEL_1_MRS_VALUE_0_1

242

MC_CHANNEL_1_MRS_VALUE_2

243

MC_CHANNEL_1_RANK_PRESENT

244

MC_CHANNEL_1_RANK_TIMING_A

245

MC_CHANNEL_1_RANK_TIMING_B

247

MC_CHANNEL_1_BANK_TIMING

248

MC_CHANNEL_1_REFRESH_TIMING

248

MC_CHANNEL_1_CKE_TIMING

249

MC_CHANNEL_1_ZQ_TIMING

250

MC_CHANNEL_1_RCOMP_PARAMS

250

MC_CHANNEL_1_ODT_PARAMS1

251

MC_CHANNEL_1_ODT_PARAMS2

252

MC_CHANNEL_1_WAQ_PARAMS

254

MC_CHANNEL_1_SCHEDULER_PARAMS

255

MC_CHANNEL_1_MAINTENANCE_OPS

255

MC_CHANNEL_1_TX_BG_SETTINGS

256

MC_CHANNEL_1_RX_BGF_SETTINGS

257

MC_CHANNEL_1_EW_BGF_SETTINGS

257

7:0 RW 0

258

Device: 4, 5

258

4.11.2 MC_DOD_CH1_0

262

MC_DOD_CH1_1

262

MC_SAG_CH0_6; MC_SAG_CH0_7

263

MC_SAG_CH1_6; MC_SAG_CH1_7

264

4.13 Memory Thermal Control

268

4.13.3 MC_THERMAL_DEFEATURE0

269

MC_THERMAL_DEFEATURE1

269

4.13.4 MC_THERMAL_PARAMS_A0

269

MC_THERMAL_PARAMS_A1

269

4.13.5 MC_THERMAL_PARAMS_B0

270

MC_THERMAL_PARAMS_B1

270

4.13.6 MC_COOLING_COEF0

270

MC_COOLING_COEF1

270

4.13.7 MC_CLOSED_LOOP0

271

MC_CLOSED_LOOP1

271

4.13.8 MC_THROTTLE_OFFSET0

271

MC_THROTTLE_OFFSET1

271

4.13.9 MC_RANK_VIRTUAL_TEMP0

272

MC_RANK_VIRTUAL_TEMP1

272

4.13.10 MC_DDR_THERM_COMMAND0

272

MC_DDR_THERM_COMMAND1

272

4.13.11 MC_DDR_THERM_STATUS0

273

MC_DDR_THERM_STATUS1

273

274 Datasheet, Volume 2

274

5 System Address Map

275

5.2 Memory Address Space

276

Misc (CPEI, etc.)

277

LocalCSR/CPUOn

277

System Address Map

278

5.2.3.1 VGA/SMM Memory Space

279

5.2.3.2 C/D/E/F Segments

280

5.2.4.1 Relocatable TSEG

281

5.2.5.1 PCI Express

281

5.2.5.2 MMIOL

282

5.2.5.3 Miscellaneous

282

5.2.5.6 Local XAPIC

283

5.2.5.7 High BIOS Area

283

5.2.5.8 INTA/Rsvd

283

5.2.5.9 Firmware

283

5.2.6.1 High System Memory

284

5.2.6.2 Memory Mapped IO High

284

5.3 IO Address Space

285

5.4 Configuration/CSR Space

286

5.5.1 SMM Space Definition

287

5.5.2 SMM Space Restrictions

288

5.5.3 SMM Space Combinations

288

5.6 Memory Shadowing

290

5.7 IIO Address Map Notes

290

5.8.1.1 General Overview

291

5.8.1.2 FWH Decoding

292

5.8.2.1 Overview

295

PCIe port

299

5.8.3 Intel

300

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