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Datasheet, Volume 2 333
Processor Configuration Registers
2.21.1 TXT.DID—TXT Device ID Register
This register contains the TXT ID for the processor.
2.21.2 TXT.DPR—DMA Protected Range Register
This is the DMA protected range register.
B/D/F/Type: 0/0/0/TXT Specific
Address Offset: 110–117h
Reset Value: 00000003A0008086h
Access: RO
Bit Attr
Reset
Value
Description
63:48 RO 0000h Reserved
47:32 RO 0003h
Revision ID (TXT.RID)
For the initial stepping of the component, the value is 0001h. The value is a
bit-mask for compatibility with prior steppings.
31:16 RO A00h
Device ID (TXT.DID)
A000h = This processor
15:0 RO 8086h
Vendor ID (TXT.VID)
This register field contains the PCI standard identification for Intel, 8086h.
B/D/F/Type: 0/0/0/TXT Specific
Address Offset: 330–337h
Reset Value: 0000000000000000h
Access: RO, RW-L, RW-L-K
Bit Attr
Reset
Value
Description
63:32 RO
00000000
h
Reserved
31:20 RO 000h
Top of DMA Protected Range (TopOfDPR)
Top address + 1 of DPR. On the processor, this is the base of TSEG. Bits 19:0
of the BASE reported here are 0_0000h.
19:12 RO 00h Reserved
11:4 RW-L 00h
DMA Protected Memory Size (DPR.SIZE)
This is the size of memory, in MB, that will be protected from DMA accesses.
A value of 00h in this field means no additional memory is protected. The
maximum amount of memory that will be protected is 255 MB.
3:1 RO 000b Reserved
0RW-L-K 0b
Lock (LOCK)
Bits 19:0 are locked down in this register when this bit is set.
This bit is a write-once bit. If BIOS writes a 0 to the bit, then it can not be
written to a 1 on subsequent writes. BIOS must write the entire register with
the correct values and set this bit with that write.
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