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Processor Configuration Registers
142 Datasheet, Volume 2
2.10.39 LCAP—Link Capabilities Register
This register indicates PCI Express device specific capabilities.
B/D/F/Type: 0/1/0/PCI
Address Offset: AC–AFh
Reset Value: 02214D02h
Access: RO, RW-O
Bit Attr
Reset
Value
Description
31:24 RO 02h
Port Number (PN)
This bit indicates the PCI Express port number for the given PCI Express link.
Matches the value in Element Self Description[31:24].
23:22 RO 00b Reserved
21 RO 1b
Reserved
Link Bandwidth Notification Capability – A value of 1b indicates support for
the Link Bandwidth Notification status and interrupt mechanisms. This
capability is required for all Root Ports and Switch downstream ports
supporting Links wider than x1 and/or multiple Link speeds.
This field is not applicable and is reserved for Endpoint devices, PCI Express
to PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification capability
must hardwire this bit to 0b.
20 RO 0b
Data Link Layer Link Active Reporting Capable (DLLLARC)
For a Downstream Port, this bit must be set to 1b if the component supports
the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine. For a hot-plug capable Downstream
Port (as indicated by the Hot-Plug Capable field of the Slot Capabilities
register), this bit must be set to 1b.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
19 RO 0b
Surprise Down Error Reporting Capable (SDERC)
For a Downstream Port, this bit must be set to 1b if the component supports
the optional capability of detecting and reporting a Surprise Down error
condition.
For Upstream Ports and components that do not support this optional
capability, this bit must be hardwired to 0b.
18 RO 0b
Clock Power Management (CPM)
A value of 1b in this bit indicates that the component tolerates the removal of
any reference clock(s) when the link is in the L1 and L2/3 Ready link states.
A value of 0b indicates the component does not have this capability and that
reference clock(s) must not be removed in these link states.
This capability is applicable only in form factors that support "clock request"
(CLKREQ#) capability.
For a multi-function device, each function indicates its capability
independently. Power Management configuration software must only permit
reference clock removal if all functions of the multifunction device indicate a
1b in this bit.
17:15 RW-O 010b
L1 Exit Latency (L1ELAT)
This field indicates the length of time this Port requires to complete the
transition from L1 to L0. The value 010 b indicates the range of 2 us to less
than 4 us.
BIOS Requirement: If this field is required to be any value other than the
default, BIOS must initialize it accordingly. Both bytes of this register that
contain a portion of this field must be written simultaneously in order to
prevent an intermediate (and undesired) value from ever existing.
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
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IKEA RENLIGFWM8 50309643 manuali
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Ikea RENLIGFWM8 50309643 Manuale Utente (60 pagine)
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Indice
FRANÇAIS 10
10
FRANÇAIS 11
11
Réglages
12
FRANÇAIS 12
12
FRANÇAIS
13
FRANÇAIS 14
14
FRANÇAIS 16
16
Programmes
16
FRANÇAIS 17
17
FRANÇAIS 18
18
FRANÇAIS 19
19
Conseils
20
FRANÇAIS 20
20
FRANÇAIS 22
22
FRANÇAIS 24
24
FRANÇAIS 25
25
FRANÇAIS 26
26
FRANÇAIS 27
27
FRANÇAIS 28
28
ITALIANO
32
ITALIANO 33
33
ITALIANO 35
35
ITALIANO 36
36
ITALIANO 37
37
ITALIANO 38
38
ITALIANO 39
39
Impostazioni
40
ITALIANO 40
40
ITALIANO 41
41
Programmi
44
ITALIANO 44
44
ITALIANO 45
45
ITALIANO 46
46
ITALIANO 47
47
ITALIANO 48
48
ITALIANO 49
49
ITALIANO 51
51
ITALIANO 52
52
ITALIANO 53
53
Dati tecnici
54
ITALIANO 54
54
ITALIANO 55
55
AA-1624346-1
60
Ikea RENLIGFWM8 50309643 Manuale Utente (60 pagine)
Marchio: Ikea | Categoria: Washing machines | Dimensione: 1.04 MB |
Indice
Contents
4
ENGLISH 10
10
Settings
11
Daily Use
11
ENGLISH 11
11
Programmes
14
ENGLISH 14
14
ENGLISH 15
15
ENGLISH 16
16
ENGLISH 17
17
ENGLISH 18
18
ENGLISH 19
19
ENGLISH 21
21
ENGLISH 22
22
ENGLISH 23
23
ENGLISH 24
24
ENGLISH 25
25
DEUTSCH 31
31
DEUTSCH 32
32
Bedienfeld
33
DEUTSCH 33
33
DEUTSCH 34
34
DEUTSCH 35
35
DEUTSCH 36
36
DEUTSCH 37
37
Programme
40
DEUTSCH 40
40
DEUTSCH 41
41
DEUTSCH 42
42
DEUTSCH 43
43
DEUTSCH 44
44
DEUTSCH 46
46
Fehlersuche
48
DEUTSCH 48
48
DEUTSCH 49
49
DEUTSCH 50
50
DEUTSCH 51
51
UMWELTTIPPS
52
DEUTSCH 52
52
DEUTSCH 55
55
AA-1624329-1
60
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