Intel NETWORK PROCESSOR IXP2800 Manuel d'utilisateur télécharger pdf (Page 421)

Hardware Reference Manual 421

Intel

IXP2800 Network Processor

Performance Monitor Unit

11.4.6.25 SRAM CH2 Events Target ID(001100) / Design Block #(0010)

11.4.6.26 SRAM CH1 Events Target ID(001101) / Design Block #(0010)

Table 179. SRAM CH3 PMU Event List

Event

Number

Event Name

Clock

Domain

Pulse/

Level

Burst Description

Note:

1. All the SRAM Channel has same event lists.

2. S_CLK = SRAM clock domain

3. P_CLK = PP clock domain

signals that begin with sps_ correspond to S_Push Arb

signals that begin with spl_ correspond to S-Pull Arb

signals that contain _pc_ (after the unit designation) correspond to the PCI target interface

signals that contain _m_ (after the unit designation) correspond to the MSF target interface

signals that contain _sh_ (after the unit designation) correspond to the SHaC target interface

signals that contain _s0_ (after the unit designation) correspond to the SRAM0 target interface

signals that contain _s1_ (after the unit designation) correspond to the SRAM1 target interface

signals that contain _s2_ (after the unit designation) correspond to the SRAM2 target interface

signals that contain _s3_ (after the unit designation) correspond to the SRAM3 target interface

Table 180. SRAM CH3 PMU Event List