Intel NETWORK PROCESSOR IXP2800 Manuel d'utilisateur

Order Number: 278882-010Intel® IXP2800 Network ProcessorHardware Reference ManualAugust 2004

10 Hardware Reference Manual Contents8.2.5 Rx_Thread_Freelist_Timeout_# ... 2

100 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.6.2.3 Cache Policies3.6.2.3.1 CacheabilityData at a specified address

Hardware Reference Manual 101Intel® IXP2800 Network ProcessorIntel XScale® Core3.6.2.3.3 Write Miss PolicyA write operation that misses the cache, req

102 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.6.2.4 Round-Robin Replacement AlgorithmThe line replacement algorithm

Hardware Reference Manual 103Intel® IXP2800 Network ProcessorIntel XScale® Core3.6.3 Data Cache and Mini-Data Cache Control3.6.3.1 Data Memory State A

104 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.6.3.3.1 Global Clean and Invalidate OperationA simple software routin

Hardware Reference Manual 105Intel® IXP2800 Network ProcessorIntel XScale® Core3.6.4 Reconfiguring the Data Cache as Data RAMSoftware has the ability

106 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.6.5 Write Buffer/Fill Buffer Operation and ControlThe write buffer is

Hardware Reference Manual 107Intel® IXP2800 Network ProcessorIntel XScale® Core3.8 Performance MonitoringThe Intel XScale® core hardware provides two

108 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreSome typical combination of counted events are listed in this section a

Hardware Reference Manual 109Intel® IXP2800 Network ProcessorIntel XScale® Core3.8.1.2 Data Cache Efficiency ModePMN0 totals the number of data cache

Hardware Reference Manual 11Contents8.7.2.3 Single IXP2800 Network Processor...2898.8 Interface t

110 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreStatistics derived from these two events:• The average number of cycles

Hardware Reference Manual 111Intel® IXP2800 Network ProcessorIntel XScale® Core3.8.1.6 Instruction TLB Efficiency ModePMN0 totals the number of instru

112 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.9.1 Interrupt LatencyMinimum Interrupt Latency is defined as the mini

Hardware Reference Manual 113Intel® IXP2800 Network ProcessorIntel XScale® Core3.9.3 Addressing ModesAll load and store addressing modes implemented i

114 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreMinimum Issue Latency (without Branch Misprediction) to the minimum bra

Hardware Reference Manual 115Intel® IXP2800 Network ProcessorIntel XScale® Core3.9.4.2 Branch Instruction Timings (3.9.4.3 Data Processing Instruction

116 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.9.4.4 Multiply Instruction TimingsTable 31. Multiply Instruction Tim

Hardware Reference Manual 117Intel® IXP2800 Network ProcessorIntel XScale® Core3.9.4.5 Saturated Arithmetic InstructionshUMULLRs[31:15] = 0x000000 1 R

118 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.9.4.6 Status Register Access Instructions3.9.4.7 Load/Store Instructi

Hardware Reference Manual 119Intel® IXP2800 Network ProcessorIntel XScale® Core3.9.4.9 Coprocessor Instructions3.9.4.10 Miscellaneous Instruction Timi

12 Hardware Reference Manual Contents9 PCI Unit...

120 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.10.1 IXP2800 Network Processor EndiannessEndianness defines the way b

Hardware Reference Manual 121Intel® IXP2800 Network ProcessorIntel XScale® Core3.10.1.1 Read and Write Transactions Initiated by the Intel XScale® Cor

122 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core16-Bit (Word) ReadWhen reading a word, the Intel XScale® core generates

Hardware Reference Manual 123Intel® IXP2800 Network ProcessorIntel XScale® Core32-Bit (Longword) Read32-bit (longword) reads are independent of endian

124 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreWord Write (16-Bits Write)When the Intel XScale® core writes a 16-bit w

Hardware Reference Manual 125Intel® IXP2800 Network ProcessorIntel XScale® Core3.11 Intel XScale® Core Gasket Unit3.11.1 OverviewThe Intel XScale® cor

126 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreThe Intel XScale® core coprocessor bus is not used in the IXP2800 Netwo

Hardware Reference Manual 127Intel® IXP2800 Network ProcessorIntel XScale® Core3.11.2 Intel XScale® Core Gasket Functional Description3.11.2.1 Command

128 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.11.4 Atomic OperationsThe Intel XScale® core has Swap (SWP) and Swap

Hardware Reference Manual 129Intel® IXP2800 Network ProcessorIntel XScale® Core3.11.4.1 Summary of Rules for the Atomic Command Regarding I/OThe follo

Hardware Reference Manual 13Contents9.4.2 Push/Pull Command Bus Target Interface...3459.4.2

130 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.11.5 I/O TransactionThe Intel XScale® core can request an I/O transac

Hardware Reference Manual 131Intel® IXP2800 Network ProcessorIntel XScale® Core3.11.7 Gasket Local CSRThere are two sets of Control and Status registe

132 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.11.8 InterruptThe Intel XScale® core CSR controller contains local CS

Hardware Reference Manual 133Intel® IXP2800 Network ProcessorIntel XScale® CoreFigure 29. Interrupt Mask Block DiagramA9699-01{Error,Thread}RawStatusI

134 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12 Intel XScale® Core Peripheral InterfaceThis section describes the

Hardware Reference Manual 135Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.1.1 Data TransfersThe current rate for data transfers is four byte

136 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.1.3 Address Spaces for XPI Internal DevicesTable 53 shows the addr

Hardware Reference Manual 137Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.2 UART OverviewThe UART performs serial-to-parallel conversion on

138 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.3 UART OperationThe format of a UART data frame is shown in Figure

Hardware Reference Manual 139Intel® IXP2800 Network ProcessorIntel XScale® CoreCharacter Time-out InterruptWhen the receiver FIFO and receiver time-ou

14 Hardware Reference Manual Contents10.3.2 PCI-Initiated Reset...

140 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.5 General Purpose I/O (GPIO)The IXP2800 Network Processor has eigh

Hardware Reference Manual 141Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.6 TimersThe IXP2800 Network Processor supports four timers. These

142 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreFigure 34 shows the Timer Internal logic.3.12.7 Slowport UnitThe IXP280

Hardware Reference Manual 143Intel® IXP2800 Network ProcessorIntel XScale® CoreThe Flash memory interface is used for the PROM device. The microproces

144 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.3 Slowport Unit InterfacesFigure 35 shows the Slowport unit inte

Hardware Reference Manual 145Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.4 Address SpaceThe total address space is defined as 64 Mbytes,

146 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.6 Slowport 8-Bit Device Bus ProtocolsThe write/read transfer pro

Hardware Reference Manual 147Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.6.1 Mode 0 Single Write Transfer for Fixed-Timed DeviceFigure 38

148 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.6.2 Mode 0 Single Write Transfer for Self-Timing DeviceFigure 39

Hardware Reference Manual 149Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.6.3 Mode 0 Single Read Transfer for Fixed-Timed DeviceFigure 40

Hardware Reference Manual 15Contents11.4.6.7 ME01 Events Target ID(100001) / Design Block #(1001) ...41011.4.6.8 ME02 Events Targe

150 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.6.4 Single Read Transfer for a Self-Timing DeviceFigure 41 demon

Hardware Reference Manual 151Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.7.1 Mode 1: 16-Bit Microprocessor Interface Support with 16-Bit

152 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreFigure 42. An Interface Topology with Lucent* TDAT042G5 SONET/SDHA9370-

Hardware Reference Manual 153Intel® IXP2800 Network ProcessorIntel XScale® Core16-Bit Microprocessor Write Interface ProtocolFigure 43 uses the Lucent

154 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core16-Bit Microprocessor Read Interface ProtocolFigure 44, likewise depict

Hardware Reference Manual 155Intel® IXP2800 Network ProcessorIntel XScale® Core3.12.7.7.2 Mode 2: Interface with 8 Data Bits and 11 Address BitsThis a

156 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CorePMC-Sierra* PM5351 S/UNI-TETRA* Write Interface ProtocolFigure 46 depic

Hardware Reference Manual 157Intel® IXP2800 Network ProcessorIntel XScale® CoreFigure 47, depicts a single read transaction launched from the IXP2800

158 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreFor a write, SP_CP loads the data onto the 74F646 (or equivalent) tri-s

Hardware Reference Manual 159Intel® IXP2800 Network ProcessorIntel XScale® CoreFigure 49. Mode 3 Second Interface Topology with Intel / AMCC* SONET/SD

16 Hardware Reference Manual ContentsFigures1 IXP2800 Network Processor Functional Block Diagram ...

160 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreMode 3 Write Interface ProtocolFigure 50 depicts a single write transac

Hardware Reference Manual 161Intel® IXP2800 Network ProcessorIntel XScale® CoreMode 3 Read Interface ProtocolFigure 51 depicts a single read transacti

162 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreIt employs the same way to pack and unpack the data between the IXP2800

Hardware Reference Manual 163Intel® IXP2800 Network ProcessorIntel XScale® CoreFigure 53. Second Interface Topology with Intel / AMCC* SONET/SDH Devic

164 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreMode 4 Write Interface ProtocolFigure 54 depicts a single write transac

Hardware Reference Manual 165Intel® IXP2800 Network ProcessorIntel XScale® CoreMode 4 Read Interface ProtocolFigure 55 shows a single read transaction

166 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core

Hardware Reference Manual 167Intel® IXP2800 Network ProcessorMicroenginesMicroengines 4This section defines the Network Processor Microengine (ME). Th

168 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroenginesFigure 56. Microengine Block DiagramB1670-01128GPRs(A Bank)decode128GPRs(B Ba

Hardware Reference Manual 169Intel® IXP2800 Network ProcessorMicroengines4.1.1 Control StoreThe Control Store is a static RAM that holds the program t

Hardware Reference Manual 17Contents48 An Interface Topology with Intel / AMCC* SONET/SDH Device ...1584

170 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroenginesThe Microengine is in Idle state whenever no Context is running (all Contexts

Hardware Reference Manual 171Intel® IXP2800 Network ProcessorMicroengines4.1.3 Datapath RegistersAs shown in the block diagram in Figure 56, each Micr

172 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroenginesTypically, the external units access the Transfer registers in response to co

Hardware Reference Manual 173Intel® IXP2800 Network ProcessorMicroenginesIt is also possible to make use of both or one LM_Addrs as global by setting

174 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroengines4.1.4.2 Absolute Addressing ModeWith Absolute addressing, any GPR can be read

Hardware Reference Manual 175Intel® IXP2800 Network ProcessorMicroenginesExample 24 shows an align sequence of instructions and the value of the vario

176 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroenginesExample 25 shows another sequence of instructions and the value of the variou

Hardware Reference Manual 177Intel® IXP2800 Network ProcessorMicroenginesNote: The State bits are data associated with the entry. State bits are only

178 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroenginesOne possible way to use the result of a lookup is to dispatch to the proper c

Hardware Reference Manual 179Intel® IXP2800 Network ProcessorMicroengines The CAM can be cleared with CAM_Clear instruction. This instruction writes 0

18 Hardware Reference Manual Contents98 CSIX Flow Control Interface — FCIFIFO and FCEFIFO in Full Duplex Mode ... 27799 CSIX F

180 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroengines4.5 Event SignalsEvent Signals are used to coordinate a program with completi

Hardware Reference Manual 181Intel® IXP2800 Network ProcessorMicroengines4.5.1 Microengine EndiannessMicroengine operation from an “endian” point of v

182 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroengines4.5.1.2 Write to TBUFData in TBUF is arranged in LWBE order. When writing fro

Hardware Reference Manual 183Intel® IXP2800 Network ProcessorMicroengines4.5.1.6 Write to Hash UnitFigure 62 explains 48-, 64-, and 128-bit hash opera

184 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroengines4.5.2.1 Read from RBUFTo analyze the endianness on the media-receive interfac

Hardware Reference Manual 185Intel® IXP2800 Network ProcessorMicroengines4.5.2.2 Write to TBUFFor writing to TBUF, the header comes from the Microengi

186 Hardware Reference ManualIntel® IXP2800 Network ProcessorMicroenginesSince data in RBUF or DRAM is arranged in LWBE order, it is swapped on the wa

Hardware Reference Manual 187Intel® IXP2800 Network ProcessorDRAMDRAM 5This section describes Rambus* DRAM operation.5.1 OverviewThe IXP2800 Network P

188 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAM5.2 Size ConfigurationEach channel can be populated with 1 – 4 RDRAMs (Short Channel

Hardware Reference Manual 189Intel® IXP2800 Network ProcessorDRAM5.3 DRAM ClockingFigure 66 shows the clock generation for one channel (this descripti

Hardware Reference Manual 19ContentsTables1 Data Terminology ...

190 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAM5.4 Bank PolicyThe RDRAM Controller uses a “closed bank” policy. Banks are activated

Hardware Reference Manual 191Intel® IXP2800 Network ProcessorDRAM5.5 InterleavingThe RDRAM channels are interleaved on 128-byte boundaries in hardware

192 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAMTable 63. Address Rearrangement for 3-Way Interleave (Sheet 1 of 2)When these bits o

Hardware Reference Manual 193Intel® IXP2800 Network ProcessorDRAMTable 64. Address Rearrangement for 3-Way Interleave (Sheet 2 of 2) (Rev B)5.5.2 Tw

194 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAM5.5.4 Interleaving Across RDRAMs and BanksIn addition to interleaving across the diff

Hardware Reference Manual 195Intel® IXP2800 Network ProcessorDRAM5.6.2 Parity EnabledOn writes, odd byte parity is computed for each byte and written

196 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAMTo avoid the detection of false ECC errors, the RDRAM ECC mode must be initialized us

Hardware Reference Manual 197Intel® IXP2800 Network ProcessorDRAM5.8 Microengine SignalsUpon completion of a read or write, the RDRAM controller can s

198 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAMSerial reads are done by the following steps:1. Read RDRAM_Serial_Command; test Busy

Hardware Reference Manual 199Intel® IXP2800 Network ProcessorDRAM5.10.1 CommandsWhen a valid command is placed on the command bus, the control logic c

2 Hardware Reference Manual Revision HistoryINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. EXCEPT AS PROVIDED IN INTEL

20 Hardware Reference Manual Contents47 Byte-Enable Generation by the Intel XScale® Core for Byte Writes in Little- and Big-Endian Systems ...

200 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAM5.10.3 DRAM ReadWhen a read (or TBUF_WR, which does a DRAM read) command is at the he

Hardware Reference Manual 201Intel® IXP2800 Network ProcessorDRAM5.10.6 ArbitrationThe channel needs to arbitrate among several different operations a

202 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAM• Supports chaining for burst DRAM push operations to tell the arbiter to grant conse

Hardware Reference Manual 203Intel® IXP2800 Network ProcessorDRAM5.11.2 DRAM Push Arbiter DescriptionThe general data flow for a push operation is as

204 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAMThe DRM Push Arbiter boundary conditions are:• Make sure each of the push_request que

Hardware Reference Manual 205Intel® IXP2800 Network ProcessorDRAMWhen a requestor gets a pull command on the CMD_BUS, the requestor sends the command

206 Hardware Reference ManualIntel® IXP2800 Network ProcessorDRAM

Hardware Reference Manual 207Intel® IXP2800 Network ProcessorSRAM InterfaceSRAM Interface 66.1 OverviewThe IXP2800 Network Processor contains four ind

208 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM Interface6.2 SRAM Interface ConfigurationsMemory is logically four bytes (one longwo

Hardware Reference Manual 209Intel® IXP2800 Network ProcessorSRAM InterfaceIn general, QDR and QDR II bursts of two SRAMs are supported at speeds up t

Hardware Reference Manual 21Contents95 Order in which Data is Transmitted from TBUF...

210 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM InterfaceEach channel can be expanded in depth according to the number of port enabl

Hardware Reference Manual 211Intel® IXP2800 Network ProcessorSRAM InterfaceA side-effect of the pipeline registers is to add latency to reads, and the

212 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM InterfaceUp to two Microengine signals are assigned to each read-modify-write refere

Hardware Reference Manual 213Intel® IXP2800 Network ProcessorSRAM Interface6.4.3 Queue Data Structure CommandsThe ability to enqueue and dequeue data

214 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM InterfaceThe ENQ_tail_and_link command followed by ENQ_tail enqueue a previously lin

Hardware Reference Manual 215Intel® IXP2800 Network ProcessorSRAM InterfaceThere are two different modes for the dequeue command. One mode removes an

216 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM InterfaceNote: For a Ring or Journal, Head and Tail must be initialized to the same

Hardware Reference Manual 217Intel® IXP2800 Network ProcessorSRAM Interface6.4.3.3 ENQ and DEQ CommandsThese commands add or remove elements from the

218 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM InterfaceNote: If incorrect parity is detected on the read portion of an atomic read

Hardware Reference Manual 219Intel® IXP2800 Network ProcessorSRAM Interface6.7 Reference OrderingThis section describes the ordering between accesses

22 Hardware Reference Manual Contents138 Byte Enable Alignment for 64-Bit PCI Data In (64 Bits PCI Little-Endian to Big-Endian with Swap)...

220 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM Interface6.7.2 Microcode Restrictions to Maintain OrderingThe microcode programmer m

Hardware Reference Manual 221Intel® IXP2800 Network ProcessorSRAM InterfaceOther microcode rules:• All access to atomic variables should be through re

222 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM InterfaceThe external coprocessor interface is based on FIFO communication.A thread

Hardware Reference Manual 223Intel® IXP2800 Network ProcessorSRAM InterfaceThere can be multiple operations in progress in the coprocessor. The SRAM c

224 Hardware Reference ManualIntel® IXP2800 Network ProcessorSRAM Interface

Hardware Reference Manual 225Intel® IXP2800 Network ProcessorSHaC — Unit ExpansionSHaC — Unit Expansion 7This section covers the operation of the Scra

226 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionFigure 84. SHaC Top Level DiagramA9751-03ScratchRAM(4 K x 32)Scratch

Hardware Reference Manual 227Intel® IXP2800 Network ProcessorSHaC — Unit Expansion7.1.2 Scratchpad7.1.2.1 Scratchpad DescriptionThe SHaC Unit contains

228 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionFigure 85. Scratchpad Block DiagramA9756-02ScratchpadStateMachineCSR

Hardware Reference Manual 229Intel® IXP2800 Network ProcessorSHaC — Unit Expansion7.1.2.2 Scratchpad InterfaceNote: The Scratchpad command and S_Push

Hardware Reference Manual 23Contents181 SRAM CH0 PMU Event List ...

230 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionIf the Command Inlet FIFO becomes full, the Scratchpad controller se

Hardware Reference Manual 231Intel® IXP2800 Network ProcessorSHaC — Unit ExpansionWhen the RMW command reaches the head of the Command pipe, the Scrat

232 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionHead, Tail, Base, and Size are registers in the Scratchpad Unit. Hea

Hardware Reference Manual 233Intel® IXP2800 Network ProcessorSHaC — Unit ExpansionThe ring commands operate as outlined in the pseudo-code in Example

234 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionFor writes using the Reflector mode, Scratchpad arbitrates for the S

Hardware Reference Manual 235Intel® IXP2800 Network ProcessorSHaC — Unit Expansion7.1.2.3.3 Clocks and ResetClock generation and distribution is handl

236 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit Expansion7.1.3 Hash UnitThe SHaC unit contains a Hash Unit that can take 48-,

Hardware Reference Manual 237Intel® IXP2800 Network ProcessorSHaC — Unit Expansion7.1.3.1 Hashing OperationUp to three hash indexes (see Example 33) c

238 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionThe Intel XScale® core initiates a hash operation by writing a set o

Hardware Reference Manual 239Intel® IXP2800 Network ProcessorSHaC — Unit ExpansionThe Hash Unit shares the Scratchpad’s Push Data FIFO. After each has

24 Hardware Reference Manual Contents

240 Hardware Reference ManualIntel® IXP2800 Network ProcessorSHaC — Unit ExpansionEquation 7. (48-bit hash operation)Equation 8. (64-bit hash oper

Hardware Reference Manual 241Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceMedia and Switch Fabric Interface 88.1 OverviewThe Media

242 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe use of some of the receive and transmit pins is base

Hardware Reference Manual 243Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.1.1 SPI-4SPI-4 is an interface for packet and cell tra

244 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceControl words are inserted only between burst transfers;

Hardware Reference Manual 245Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceTable 84 shows the order of bytes on SPI-4; this example

246 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.1.2 CSIXCSIX_L1 (Common Switch Interface) defines an i

Hardware Reference Manual 247Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2 ReceiveThe receive section consists of:• Receive Pin

248 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2.1 Receive PinsThe use of the receive pins is a funct

Hardware Reference Manual 249Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe data in each partition is further broken up into ele

Hardware Reference Manual 25Intel® IXP2800 Network Processor IntroductionIntroduction 11.1 About This DocumentThis document is the hardware reference

250 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe src_op_1 and src_op_2 operands are added together to

Hardware Reference Manual 251Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceSection 8.2.7.1). The SPI-4 Control Word Type, EOPS, SOP

252 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe status contains the following information:The defini

Hardware Reference Manual 253Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2.2.2 CSIXCSIX CFrames are placed into either RBUF or

254 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceNote: In CSIX protocol, an RBUF element is allocated onl

Hardware Reference Manual 255Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2.3 Full Element ListReceive control hardware maintain

256 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2.5 Rx_Thread_Freelist_Timeout_#Each Rx_Thread_Freelis

Hardware Reference Manual 257Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceWhen an mpacket becomes valid as described in Section 8.

258 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceTable 93 summarizes the differences in RBUF operation be

Hardware Reference Manual 259Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceWhen MSF_RX_CONTROL[RX_Calendar_Mode] is set to Force_Ov

26 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntroduction1.3 TerminologyTable 1 and Table 2 list the terminology used in this manual.Ta

260 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2.7.2.2 Virtual Output QueueCSIX protocol provides Vir

Hardware Reference Manual 261Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.2.8.2 CSIX8.2.8.2.1 Horizontal ParityThe receive logic

262 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3 TransmitThe transmit section consists of:• Transmit

Hardware Reference Manual 263Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.2 TBUFThe TBUF is a RAM that holds data and status t

264 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceTable 97 shows the TBUF partition options. Note that the

Hardware Reference Manual 265Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfacePayload Offset — Number of bytes to skip from the last 6

266 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.2.1 SPI-4For SPI-4, data is put into the data portio

Hardware Reference Manual 267Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.2.2 CSIXFor CSIX protocol, the TBUF should be set to

268 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.3 Transmit Operation SummaryDuring transmit processi

Hardware Reference Manual 269Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceIf the next sequential element is not valid when its tur

Hardware Reference Manual 27Intel® IXP2800 Network ProcessorTechnical DescriptionTechnical Description 22.1 OverviewThis section provides a brief over

270 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceNote: A Dead Cycle is any cycle after the end of a CFram

Hardware Reference Manual 271Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.4.1 SPI-4FIFO status information is sent periodicall

272 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe TX_Port_Status_# or the TX_Multiple_Port_Status_# re

Hardware Reference Manual 273Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.4.2 CSIXThere are two types of CSIX flow control:• L

274 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.3.5.2 CSIX8.3.5.2.1 Horizontal ParityThe transmit logi

Hardware Reference Manual 275Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.5 CSIX Flow Control InterfaceThis section describes th

276 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe information transmitted on TXCSRB can be read in FC_

Hardware Reference Manual 277Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.5.2.1 Full Duplex CSIXIn Full Duplex Mode, the informa

278 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe FCIFIFO supplies two signals to Microengines, which

Hardware Reference Manual 279Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe TXCSRB and RXCSRB pins are not used in Simplex Mode.

28 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionFigure 1. IXP2800 Network Processor Functional Block DiagramA9226-02

280 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.5.3 TXCDAT/RXCDAT, TXCSOF/RXCSOF, TXCPAR/RXCPAR,and TX

Hardware Reference Manual 281Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe IXP2800 Network Processor supports all three methods

282 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.6.1 Data Training PatternThe data pin training sequenc

Hardware Reference Manual 283Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe training sequence when the pins are used for SPI-4 S

284 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe second case is when the Switch Fabric or SPI-4 frami

Hardware Reference Manual 285Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe IXP2800 Network Processor needs training at reset, o

286 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceTable 112 lists the steps to initiate the training. CSIX

Hardware Reference Manual 287Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.7 CSIX Startup SequenceThis section defines the sequen

288 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.7.1.3 Single IXP2800 Network Processor1. The Microengi

Hardware Reference Manual 289Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.7.2.2 Egress IXP2800 Network Processor1. On reset, FC_

Hardware Reference Manual 29Intel® IXP2800 Network ProcessorTechnical DescriptionFigure 2. IXP2800 Network Processor Detailed DiagramA9750-03SHaC Uni

290 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.8 Interface to Command and Push and Pull BusesFigure 1

Hardware Reference Manual 291Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN Regis

292 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.8.5 From DRAM to TBUF for Instruction:dram[tbuf_wr, --

Hardware Reference Manual 293Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceSPI-4.2 supports up to 256 port addresses, with independ

294 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe SPI-4.2 mode of the simplex configuration supports a

Hardware Reference Manual 295Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.1.3 Dual Network Processor Full Duplex Configuration

296 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.1.4 Single Network Processor Full Duplex Configurati

Hardware Reference Manual 297Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.1.5 Single Network Processor, Full Duplex Configurat

298 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.2.1 Framer, Single Network Processor Ingress and Egr

Hardware Reference Manual 299Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.2.3 Framer, Single Network Processor Ingress and Egr

Hardware Reference Manual 3ContentsContents1 Introduction...

30 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.2 Intel XScale® Core MicroarchitectureThe Intel XScale® microarchit

300 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.2.5 Framer, Single Network Processor, Co-Processor,

Hardware Reference Manual 301Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.3 SPI-4.2 SupportData is transferred across the SPI-

302 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceAs threads complete processing of the data in a buffer,

Hardware Reference Manual 303Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.4 CSIX-L1 Protocol Support8.9.4.1 CSIX-L1 Interface

304 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceInformation is passed across the interface in CFrames. C

Hardware Reference Manual 305Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe network processor supports a variation of the standa

306 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe backpressure signal (TXCFC, RXCFC) is an asynchronou

Hardware Reference Manual 307Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe transfer time of CFrames across the RPCI is four tim

308 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe SPI-4.2 interface does not support a virtual output

Hardware Reference Manual 309Intel® IXP2800 Network ProcessorMedia and Switch Fabric InterfaceThe training pattern for the flow control data signals c

Hardware Reference Manual 31Intel® IXP2800 Network ProcessorTechnical Description2.2.2.4 Branch Target BufferThe Intel XScale® microarchitecture provi

310 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.4.4 CSIX-L1 Protocol Transmitter SupportThe Intel® I

Hardware Reference Manual 311Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.4.5 Implementation of a Bridge Chip to CSIX-L1The In

312 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.5 Dual Protocol (SPI and CSIX-L1) SupportIn many sys

Hardware Reference Manual 313Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.5.3 Implementation of a Bridge Chip to CSIX-L1 and S

314 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.6 Transmit State MachineTable 114 describes the tran

Hardware Reference Manual 315Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.6.2 Training Transmitter State MachineThe Training S

316 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.7 Dynamic De-SkewThe Intel® IXP2800 Network Processo

Hardware Reference Manual 317Intel® IXP2800 Network ProcessorMedia and Switch Fabric Interface8.9.8 Summary of Receiver and Transmitter SignalsFigure

318 Hardware Reference ManualIntel® IXP2800 Network ProcessorMedia and Switch Fabric Interface

Hardware Reference Manual 319Intel® IXP2800 Network ProcessorPCI UnitPCI Unit 9This section contains information on the IXP2800 Network Processor PCI

32 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.2.2.7 Address MapFigure 3 shows the partitioning of the Intel XScal

320 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitFigure 118. PCI Functional BlocksA9765-01InitiatorAddress FIFOInitiatorRead FIFOI

Hardware Reference Manual 321Intel® IXP2800 Network ProcessorPCI Unit9.2 PCI Pin Protocol Interface BlockThis block generates the PCI compliant protoc

322 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitIf a read address is latched, the subsequent cycles will be retried and no addres

Hardware Reference Manual 323Intel® IXP2800 Network ProcessorPCI UnitPCI functions not supported by the PCI Unit include:• IO Space response as a targ

324 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.2.2.1 Initialization by the Intel XScale® CoreThe PCI unit is initialized to an

Hardware Reference Manual 325Intel® IXP2800 Network ProcessorPCI Unit9.2.3 PCI Type 0 Configuration Cycles A PCI access to a configuration register oc

326 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.2.5 PCI Target CyclesThe following PCI transactions are not supported by the PC

Hardware Reference Manual 327Intel® IXP2800 Network ProcessorPCI Unit9.2.5.5 Target Read Accesses from the PCI BusA PCI read occurs if the PCI address

328 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unitnever de-asserts it prior to receiving gnt_l[0] or de-asserts it after receiving

Hardware Reference Manual 329Intel® IXP2800 Network ProcessorPCI Unit9.2.6.6 Special CycleAs an initiator, special cycles are broadcast to all PCI age

Hardware Reference Manual 33Intel® IXP2800 Network ProcessorTechnical Description2.3 MicroenginesThe Microengines do most of the programmable pre-pack

330 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.2.11 PCI Central FunctionsThe CFG_RSTDIR pin is active high for enabling the P

Hardware Reference Manual 331Intel® IXP2800 Network ProcessorPCI Unit9.2.11.3 PCI Internal ArbiterThe PCI unit contains a PCI bus arbiter that support

332 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.3 Slave Interface BlockThe slave interface logic supports internal slave device

Hardware Reference Manual 333Intel® IXP2800 Network ProcessorPCI Unit9.3.2 SRAM InterfaceThe SRAM interface connects the FBus to the internal push/pul

334 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.3.2.2 SRAM Slave ReadsFor a slave read from SRAM, a 32-bit DWORD is fetched fro

Hardware Reference Manual 335Intel® IXP2800 Network ProcessorPCI Unit9.3.3.2 DRAM Slave ReadsFor target reads from IXP2800 Network Processor memory, t

336 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitNote: The IXP2800/IXP2850 always disconnects after transferring 16-bytes for DRAM

Hardware Reference Manual 337Intel® IXP2800 Network ProcessorPCI UnitThe doorbell interrupts are controlled through the registers shown in Table 124.T

338 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitThe Doorbell Setup register allows the Intel XScale® core and a PCI device to per

Hardware Reference Manual 339Intel® IXP2800 Network ProcessorPCI Unit9.3.5 PCI Interrupt Pin An external PCI interrupt can be generated in the followi

34 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionFigure 4. Microengine Block DiagramB1670-01128GPRs(A Bank)decode128G

340 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.4 Master Interface BlockThe Master Interface consists of the DMA engine and the

Hardware Reference Manual 341Intel® IXP2800 Network ProcessorPCI Unit9.4.1.1 Allocation of the DMA ChannelsStatic allocation are employed such that th

342 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.4.1.3 DMA DescriptorEach descriptor occupies four 32-bit Dwords and is aligned

Hardware Reference Manual 343Intel® IXP2800 Network ProcessorPCI Unit9.4.1.4 DMA Channel OperationSince a PCI device, Microengine, or the Intel XScale

344 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.4.1.5 DMA Channel End Operation1. Channel owned by PCI:If not masked via the PC

Hardware Reference Manual 345Intel® IXP2800 Network ProcessorPCI UnitA 64-bit double Dword with byte enables is pushed into the FBus FIFO from the DMA

346 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.4.2.2 Command Bus Master Access to Local Control and Status RegistersThese are

Hardware Reference Manual 347Intel® IXP2800 Network ProcessorPCI Unit9.4.2.3.2 PCI Address Generation for Configuration CyclesWhen a push/pull command

348 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.5 PCI Unit Error Behavior9.5.1 PCI Target Error Behavior9.5.1.1 Target Access H

Hardware Reference Manual 349Intel® IXP2800 Network ProcessorPCI Unit9.5.1.5 Target Write Access Receives Bad Parity PCI_PAR with the Data1. If PCI_CM

Hardware Reference Manual 35Intel® IXP2800 Network ProcessorTechnical Description2.3.1 Microengine Bus ArrangementThe IXP2800 Network Processor suppor

350 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.5.2.2 DMA Read from SRAM (Descriptor Read) Gets a Memory Error1. Set PCI_CONTRO

Hardware Reference Manual 351Intel® IXP2800 Network ProcessorPCI Unit9.5.2.5 DMA Transfer Experiences a Master Abort (Time-Out) on PCI Note: That is,

352 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI Unit9.5.3.3 Master from the Intel XScale® Core or Microengine Transfer(Write to PCI)

Hardware Reference Manual 353Intel® IXP2800 Network ProcessorPCI Unit--Table 130. Byte Lane Alignment for 64-Bit PCI Data In (64 Bits PCI Little-Endia

354 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitTable 134. Byte Lane Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI

Hardware Reference Manual 355Intel® IXP2800 Network ProcessorPCI UnitThe BE_DEMI bit of the PCI_CONTROL register can be set to enable big-endian on th

356 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitTable 141. Byte Enable Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian t

Hardware Reference Manual 357Intel® IXP2800 Network ProcessorPCI UnitThe BE_BEMI bit of the PCI_CONTROL register can be set to enable big-endian on th

358 Hardware Reference ManualIntel® IXP2800 Network ProcessorPCI UnitTable 146. PCI I/O Cycles with Data Swap EnableStepping DescriptionA SteppingA PC

Hardware Reference Manual 359Intel® IXP2800 Network ProcessorClocks and ResetClocks and Reset 10This section describes the IXP2800 Network Processor c

36 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionEach of the eight Contexts is in one of four states.1. Inactive — Som

360 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and ResetFigure 130. Overall Clock Generation and DistributionA9777-02Scratch,Hash

Hardware Reference Manual 361Intel® IXP2800 Network ProcessorClocks and ResetThe fast frequency on the IXP2800 Network Processor is generated by an on

362 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and ResetFigure 131 shows the clocks generation circuitry for the IXP2800 Network

Hardware Reference Manual 363Intel® IXP2800 Network ProcessorClocks and Reset10.2 Synchronization Between Frequency DomainsDue to the internal design

364 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and Reset10.3 ResetThe IXP2800 Network Processor can be reset four ways.• Hardware

Hardware Reference Manual 365Intel® IXP2800 Network ProcessorClocks and Reset“reset_out_strap” is sampled as 0 on the trailing edge of reset, nRESET_O

366 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and Reset10.3.2 PCI-Initiated Reset CFG_RST_DIR is not asserted and PCI_RST_L is a

Hardware Reference Manual 367Intel® IXP2800 Network ProcessorClocks and Reset10.3.3.1 Slave Network Processor (Non-Central Function)•If the Watchdog t

368 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and ResetOnce in operation, if the watchdog timer expires with watchdog timer enab

Hardware Reference Manual 369Intel® IXP2800 Network ProcessorClocks and ResetTable 149. IXP2800 Network Processor Strap PinsSignal Name DescriptionCFG

Hardware Reference Manual 37Intel® IXP2800 Network ProcessorTechnical DescriptionThe Microengine provides the following functionality during the Idle

370 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and ResetTable 150 lists the supported Strap combinations of CFG_PROM_BOOT, CFG_RS

Hardware Reference Manual 371Intel® IXP2800 Network ProcessorClocks and ResetFigure 135. Boot ProcessA9782-03No YesReset Signal asserted(hardware, sof

372 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and Reset10.4.1 Flash ROMAt power up, if FLASH_ROM is present, strap pin CFG_PROM_

Hardware Reference Manual 373Intel® IXP2800 Network ProcessorClocks and Resetcode is written in DRAM, PCI host writes 1 at bit [8] of Misc_Control reg

374 Hardware Reference ManualIntel® IXP2800 Network ProcessorClocks and Reset

Hardware Reference Manual 375Intel® IXP2800 Network ProcessorPerformance Monitor UnitPerformance Monitor Unit 1111.1 IntroductionThe Performance Monit

376 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.1.2 Motivation for Choosing CHAP CountersThe Chipset Hardware

Hardware Reference Manual 377Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.1.3 Functional Overview of CHAP CountersAt the heart of the CH

378 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.1.4 Basic Operation of the Performance Monitor UnitAt power-up

Hardware Reference Manual 379Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.1.5 Definition of CHAP TerminologyFigure 138. Basic Block Diag

38 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Descriptionmethods to write TRANSFER_IN registers, for example a read instructio

380 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.1.6 Definition of Clock DomainsThe following abbreviations are

Hardware Reference Manual 381Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.2.1 APB PeripheralThe APB is part of the AMD* controller Bus A

382 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unitacknowledge signal (CAP_CSR_RD_RDY). When the data is returned, C

Hardware Reference Manual 383Intel® IXP2800 Network ProcessorPerformance Monitor UnitTable 152. Hardware Blocks and Their Performance Measurement Even

384 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor UnitChassis/Push-PullCommand Bus UtilizationThese statistics give the

Hardware Reference Manual 385Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4 Events Monitored in HardwareTables in this section describe

386 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.3 Design Block Select DefinitionsOnce an event is defined, i

Hardware Reference Manual 387Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.4 Null EventNot an actual event. When used as an increment o

388 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.5 Threshold EventsThese are the outputs of the threshold com

Hardware Reference Manual 389Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6 External Input Events11.4.6.1 XPI Events Target ID(000001)

Hardware Reference Manual 39Intel® IXP2800 Network ProcessorTechnical Description2.3.4.4 Local Memory Local Memory is addressable storage within the M

390 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit26 TURNA0_C_P APB_CLK single separateIt enters the termination st

Hardware Reference Manual 391Intel® IXP2800 Network ProcessorPerformance Monitor Unit48 SETUP2_4_P APB_CLK single separateIt enters the pulse width of

392 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit70 TURNA3_8_P APB_CLK single separateIt enters the turnaround sta

Hardware Reference Manual 393Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.2 SHaC Events Target ID(000010) / Design Block #(0101)Tabl

394 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit22 Scratch Ring_1 Status P_CLK single separateIf SCRATCH_RING_BAS

Hardware Reference Manual 395Intel® IXP2800 Network ProcessorPerformance Monitor Unit35 Scratch Ring_14 Status P_CLK single separateIf SCRATCH_RING_BA

396 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.3 IXP2800 Network Processor MSF Events Target ID(000011) /

Hardware Reference Manual 397Intel® IXP2800 Network ProcessorPerformance Monitor Unit19 reserved20S_PULL data FIFO 1 enqueueP_CLK pulse separate21S_PU

398 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit45 Detect FC_DEAD MRX_CLK level separateIndicates that a dead cyc

Hardware Reference Manual 399Intel® IXP2800 Network ProcessorPerformance Monitor Unit70 SPI-4 Packet received P_CLK pulse separateIndicates that the S

4 Hardware Reference Manual Contents2.6 Scratchpad Memory...

40 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionAs shown in Example 1, there is a latency in loading LM_ADDR. Until t

400 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit97 Rx null autopush P_CLK pulse separate98 Tx skip P_CLK pulse se

Hardware Reference Manual 401Intel® IXP2800 Network ProcessorPerformance Monitor Unit115 FCE receive active MR_CLK level separateIndicates a valid Fl

402 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.4 Intel XScale® Core Events Target ID(000100) / Design Blo

Hardware Reference Manual 403Intel® IXP2800 Network ProcessorPerformance Monitor Unit32 reserved33 reserved34 XG_CFIFO_EMPTYN_CPP P_CLK single separat

404 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit71 XG_SRAM_WR_2_CPP P_CLK single separate XG SRAM write length=2

Hardware Reference Manual 405Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.5 PCI Events Target ID(000101) / Design Block #(1000)110 X

406 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit13 PCI_TGT_WBUF_NEMPTY P_CLK single separate PCI Target Write Buf

Hardware Reference Manual 407Intel® IXP2800 Network ProcessorPerformance Monitor Unit52 PCI_DRAM_BURST_WRITE P_CLK single separate PCI Burst Write to

408 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit89 PCI_XS_CFG_RD P_CLK single separatePCI Intel XScale® Core Read

Hardware Reference Manual 409Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.6 ME00 Events Target ID(100000) / Design Block #(1001)118

Hardware Reference Manual 41Intel® IXP2800 Network ProcessorTechnical DescriptionIn Example 8, the second instruction will access the Local Memory loc

410 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.7 ME01 Events Target ID(100001) / Design Block #(1001)12 M

Hardware Reference Manual 411Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.8 ME02 Events Target ID(100010) / Design Block #(1001)11.4

412 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.10 ME04 Events Target ID(100100) / Design Block #(1001)11.

Hardware Reference Manual 413Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.12 ME06 Events Target ID(100110) / Design Block #(1001)11.

414 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.14 ME10 Events Target ID(110000) / Design Block #(1010)11.

Hardware Reference Manual 415Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.16 ME12 Events Target ID(110010) / Design Block #(1010)11.

416 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.18 ME14 Events Target ID(110100) / Design Block #(1010)11.

Hardware Reference Manual 417Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.20 ME16 Events Target ID(100110) / Design Block #(1010)11.

418 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.22 SRAM DP1 Events Target ID(001001) / Design Block #(0010

Hardware Reference Manual 419Intel® IXP2800 Network ProcessorPerformance Monitor Unit13 sps_s0_enq_wph P_CLK single separateSRAM0 Push Command Queue F

42 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.3.5.2 Absolute Addressing ModeWith Absolute addressing, any GPR can

420 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.24 SRAM CH3 Events Target ID(001011) / Design Block #(0010

Hardware Reference Manual 421Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.25 SRAM CH2 Events Target ID(001100) / Design Block #(0010

422 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.27 SRAM CH0 Events Target ID(001110) / Design Block #(0010

Hardware Reference Manual 423Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.28 DRAM DPLA Events Target ID(010010) / Design Block #(001

424 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.29 DRAM DPSA Events Target ID(010011) / Design Block #(001

Hardware Reference Manual 425Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.30 IXP2800 Network Processor DRAM CH2 Events Target ID(010

426 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit14 deq_push_ctrl_wph P_CLK single separateActive when dequeueing

Hardware Reference Manual 427Intel® IXP2800 Network ProcessorPerformance Monitor Unit33 DAP_DEQ_B3_DATA_RPH P_CLK single separateIndicates pull data a

428 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit57 reserved58 reserved59 deq_split_cmd_fifo_wph P_CLK single sepa

Hardware Reference Manual 429Intel® IXP2800 Network ProcessorPerformance Monitor Unit11.4.6.31 IXP2800 Network Processor DRAM CH1 Events Target ID(010

Hardware Reference Manual 43Intel® IXP2800 Network ProcessorTechnical Description2.3.6 Local CSRsLocal Control and Status registers (CSRs) are externa

430 Hardware Reference ManualIntel® IXP2800 Network ProcessorPerformance Monitor Unit

44 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionExample 10 shows a big-endian align sequence of instructions and the

Hardware Reference Manual 45Intel® IXP2800 Network ProcessorTechnical DescriptionExample 11 shows a little-endian sequence of instructions and the val

46 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionNote: The State bits are data associated with the entry. The use is o

Hardware Reference Manual 47Intel® IXP2800 Network ProcessorTechnical DescriptionThe value in the State bits for an entry can be written, without modi

48 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionAn algorithm for debug software to find out the contents of the CAM i

Hardware Reference Manual 49Intel® IXP2800 Network ProcessorTechnical Description2.3.9 Event SignalsEvent Signals are used to coordinate a program wit

Hardware Reference Manual 5Contents3.2.7 Power Management...

50 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.4 DRAMThe IXP2800 Network Processor has controllers for three Rambu

Hardware Reference Manual 51Intel® IXP2800 Network ProcessorTechnical Description2.4.2 Read and Write AccessThe minimum DRAM physical access length is

52 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.5.1 QDR Clocking SchemeThe controller drives out two pairs of K clo

Hardware Reference Manual 53Intel® IXP2800 Network ProcessorTechnical DescriptionEach channel can be expanded by depth according to the number of port

54 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.5.4 Queue Data Structure CommandsThe ability to enqueue and dequeue

Hardware Reference Manual 55Intel® IXP2800 Network ProcessorTechnical DescriptionVerification is required to test only the order rules shown in Table

56 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.5.5.2 Microengine Software Restrictions to Maintain OrderingIt is t

Hardware Reference Manual 57Intel® IXP2800 Network ProcessorTechnical Description2.6.1 Scratchpad Atomic OperationsIn addition to normal reads and wri

58 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionHead, Tail, and Size are registers in the Scratchpad Unit. Head and T

Hardware Reference Manual 59Intel® IXP2800 Network ProcessorTechnical Description2.7 Media and Switch Fabric InterfaceThe Media and Switch Fabric (MSF

6 Hardware Reference Manual Contents3.6.2.3.4 Write-Back versus Write-Through... 1013.6.2.4 Round-Robin Replace

60 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionAn alternate system configuration is shown in the block diagram in Fi

Hardware Reference Manual 61Intel® IXP2800 Network ProcessorTechnical Description2.7.2 CSIXCSIX-L1 (Common Switch Interface) defines an interface betw

62 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.7.3.1 RBUFRBUF is a RAM that holds received data. It stores receive

Hardware Reference Manual 63Intel® IXP2800 Network ProcessorTechnical Description2.7.3.1.2 CSIX and RBUFCSIX CFrames are placed into either RBUF with

64 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionEach RX_THREAD_FREELIST has an associated countdown timer. If the tim

Hardware Reference Manual 65Intel® IXP2800 Network ProcessorTechnical Description2.7.4 TransmitFigure 13 is a simplified Block Diagram of the MSF tran

66 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionAll elements within a TBUF partition are transmitted in the order. Co

Hardware Reference Manual 67Intel® IXP2800 Network ProcessorTechnical Description2.7.4.1.2 CSIX and TBUFFor CSIX, payload information is put into the

68 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionThere is a Transmit Valid bit per element, that marks the element as

Hardware Reference Manual 69Intel® IXP2800 Network ProcessorTechnical Description2.8 Hash UnitThe IXP2800 Network Processor contains a Hash Unit that

Hardware Reference Manual 7Contents3.11.5 I/O Transaction ...

70 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionFigure 14. Hash Unit Block DiagramA9367-0212848-bit, 64-bit or 128-bi

Hardware Reference Manual 71Intel® IXP2800 Network ProcessorTechnical Description2.9 PCI ControllerThe PCI Controller provides a 64-bit, 66 MHz capabl

72 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionFor PCI to DRAM transfers, the PCI command is Memory Read, Memory Rea

Hardware Reference Manual 73Intel® IXP2800 Network ProcessorTechnical Description2.9.3.2 DMA Channel OperationThe DMA channel can be set up to read th

74 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.9.3.3 DMA Channel End Operation1. Channel owned by PCI:If not maske

Hardware Reference Manual 75Intel® IXP2800 Network ProcessorTechnical Description(either a PCI interrupt or an Intel XScale® core interrupt). When an

76 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical Description2.10 Control and Status Register Access ProxyThe Control and Status R

Hardware Reference Manual 77Intel® IXP2800 Network ProcessorTechnical Description2.11.2 TimersThe IXP2800 Network Processor contains four programmable

78 Hardware Reference ManualIntel® IXP2800 Network ProcessorTechnical DescriptionThe access is asynchronous. Insertion of delay cycles for both data s

Hardware Reference Manual 79Intel® IXP2800 Network ProcessorIntel XScale® CoreIntel XScale® Core 3This section contains information describing the Int

8 Hardware Reference Manual Contents4.3.1 Byte Align...

80 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.2 FeaturesFigure 16 shows the major functional blocks of the Intel XSc

Hardware Reference Manual 81Intel® IXP2800 Network ProcessorIntel XScale® Core3.2.3 Instruction CacheThe Intel XScale® core implements a 32-Kbyte, 32-

82 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.3 Memory ManagementThe Intel XScale® core implements the Memory Manage

Hardware Reference Manual 83Intel® IXP2800 Network ProcessorIntel XScale® Core3.3.1.2.2 Instruction CacheWhen examining these bits in a descriptor, th

84 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreIf the Line Allocation Policy is read-allocate, all load operations that

Hardware Reference Manual 85Intel® IXP2800 Network ProcessorIntel XScale® Core3.3.3 Interaction of the MMU, Instruction Cache, and Data CacheThe MMU,

86 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.3.4.3 Locking EntriesIndividual entries can be locked into the instruc

Hardware Reference Manual 87Intel® IXP2800 Network ProcessorIntel XScale® CoreThe proper procedure for locking entries into the data TLB is shown in E

88 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreFigure 17 illustrates locked entries in TLB.3.4 Instruction CacheThe Int

Hardware Reference Manual 89Intel® IXP2800 Network ProcessorIntel XScale® CoreThe instruction cache is virtually addressed and virtually tagged. The v

Hardware Reference Manual 9Contents6.2.1 Internal Interface...

90 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.4.1.2 Operation when Instruction Cache is DisabledDisabling the cache

Hardware Reference Manual 91Intel® IXP2800 Network ProcessorIntel XScale® Core3.4.1.5 Parity ProtectionThe instruction cache is protected by parity to

92 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.4.2 Instruction Cache Control3.4.2.1 Instruction Cache State at ResetA

Hardware Reference Manual 93Intel® IXP2800 Network ProcessorIntel XScale® CoreThere are several requirements for locking down code:1. The routine used

94 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® CoreExample 20 shows how a routine, called “lockMe” in this example, might b

Hardware Reference Manual 95Intel® IXP2800 Network ProcessorIntel XScale® CoreThe BTB takes the current instruction address and checks to see if this

96 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.5.2 Update PolicyA new entry is stored into the BTB when the following

Hardware Reference Manual 97Intel® IXP2800 Network ProcessorIntel XScale® Core3.6.1 Overviews3.6.1.1 Data Cache OverviewThe data cache is a 32-Kbyte,

98 Hardware Reference ManualIntel® IXP2800 Network ProcessorIntel XScale® Core3.6.1.2 Mini-Data Cache OverviewThe mini-data cache is a 2-Kbyte, 2-way

Hardware Reference Manual 99Intel® IXP2800 Network ProcessorIntel XScale® Core3.6.1.3 Write Buffer and Fill Buffer OverviewThe Intel XScale® core empl