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Pentium
®
II Processor at 350 MHz, 400 MHz, and 450 MHz
Datasheet 37
3.1 System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines
Table 21 describes the signal quality specifications at the processor core for the Pentium II
processor system bus clock (BCLK) signal. Table 22 describes guidelines for signal quality
measurement at the processor edge fingers. Figure 13 describes the signal quality waveform for the
system bus clock at the processor core pins. Figure 14 describes the signal quality waveform for the
system bus clock at the processor edge fingers.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium
®
II processor frequencies and cache sizes.
2. This is the Pentium II processor system bus clock overshoot and undershoot specification for 100-MHz system bus
operation.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage
the BCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits. This specification is an
absolute value.
Table 21. BCLK Signal Quality Specifications for Simulation at the Processor Core
1
T# Parameter Min Nom Max Unit Fi
g
ure Notes
V1: BCLK V
IL
0.5 V 13
V2: BCLK V
IH
2.0 V 13 2
V3: V
IN
Absolute Voltage Range –0.7 3.3 V 13 2
V4: Rising Edge Ringback 1.7 V 13 3
V5: Falling Edge Ringback 0.7 V 13 3
Figure 13. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
V2
V1
V3
V3
T3
V5
V4
T6 T4 T5
Voltage
Time
V2
V1
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