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Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 2 57
Functional Description
3 Functional Description
This chapter describes the functional differences between the Intel Xeon processor
5500 series and Intel Xeon processor 5600 series. For more information on the Intel
Xeon processor 5500 series features and functionality, refer to the Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 2.
3.1 Integrated Memory Controller
The Intel Xeon processor 5600 series integrated memory controller supports DDR3
800, DDR3 1066 and DDR3 1333 memory technologies. Below is a comparison of Intel
Xeon processor 5500 series and Intel Xeon processor 5600 series memory controller
features.
Table 3-1. Integrated Memory Controller Feature Comparison (Sheet 1 of 2)
Feature Intel
®
Xeon
®
Processor 5500 Series Intel
®
Xeon
®
Processor 5600 Series
DRAM Technology DDR3
DIMM Technology RDIMM, UDIMM (1.5 V) RDIMM, UDIMM (1.5 V and 1.35 V)
DIMM Raw Cards RDIMM Raw Cards as defined by JEDEC:
A(1Rx8), B(2Rx8), C(1Rx4), D(2Rx4),
E/J(2Rx4), F/AB(4Rx4), H(4Rx8)
UDIMM Raw Cards as defined by JEDEC:
A(1Rx8), B(2Rx8), C(1Rx16), D(1Rx8 w/
ECC), E(2Rx8 w/ ECC)
RDIMM Raw Cards as defined by JEDEC:
A(1Rx8), B(2Rx8), C(1Rx4), D(2Rx4),
E/J(2Rx4), F/AB(4Rx4), H(4Rx8), D(2Rx4)
UDIMM Raw Cards as defined by JEDEC:
A(1Rx8), B(2Rx8), C(1Rx16), D(1Rx8 w/
ECC), E(2Rx8 w/ ECC)
Max Physical Channels per Socket 3
Max DIMMs per channel 2-3 RDIMMs, 2 UDIMMs
Max Speed 800, 1066, or 1333 MT/s
Max #of Ranks per Channel 8
Banks per Rank 8
DRAM Sizes 1 Gb, 2 Gb 1 Gb, 2 Gb, 4 Gb
5
Ranks per DIMM 1,2,4
Data lines per DRAM RDIMM: x4,x8; UDIMM: x8 and x16
1
Max Memory Supported per
Platform
RDIMM: 72 GB (1Rank, 18x4 GB, @800
MT/s); 144 GB (2Rank, 18x8 GB, @800
MT/s); 192 GB (4Rank, 12x16 GB, @800
MT/s)
UDIMM: 24 GB (1Rank, 12x2 GB, @1066
MT/s); 48 GB (2Rank, 12x4 GB @1066
MT/s)
RDIMM: 72 GB (1Rank, 18x4 GB, @800
MT/s); 288 GB (2Rank, 18x 16 GB, @800
MT/s); 192 GB (4Rank, 12x16 GB, @800
MT/s)
UDIMM: 24 GB (1Rank, 12x2 GB, @1066
MT/s); 48 GB (2Rank, 12x4 GB @1066
MT/s)
Address Fault Detection Address Parity
Page Policy Open and Closed Page
Intel
®
TXT (Trusted Execution) No Yes
ECC Support Yes
Independent Channel Support Yes
RAS - Lockstep Channel Support Only Channel 0 and 1 can be populated.
Not supported with Mirroring
Only Channel 0 and 1 can be populated.
Not supported with Mirroring
- Processor 5600 Series 1
- Contents 3
- Revision History 6
- 1 Introduction 7
- Introduction 8
- 2 Register Description 9
- 2.3 Device Mapping 11
- Control Registers 25
- Address Registers 26
- Rank Registers 27
- Thermal Control Registers 28
- 2.5 PCI Standard Registers 36
- 2.6.1 DESIRED_CORES 37
- 2.6.2 MIRROR_PORT_CTL 38
- 2.7.1 SAD_MCSEG_BASE 39
- 2.7.2 SAD_MCSEG_MASK 39
- 2.7.3 SAD_MESEG_BASE 39
- 2.8 Intel QPI Link Registers 40
- 2.8.2 QPI_RMT_QPILP1_STAT_L0 41
- QPI_RMT_QPILP1_STAT_L1 41
- 2.8.3 MIP_PH_CTR_L0 41
- MIP_PH_CTR_L1 41
- 2.8.4 MIP_PH_PRT_L0 42
- MIP_PH_PRT_L1 42
- 2.9.2 MC_SMI__CNTRL 43
- 2.9.3 MC_MAX_DOD 44
- 2.9.4 MC_RD_CRDT_INIT 45
- 2.9.5 MC_SCRUBADDR_HI 46
- 2.10.1 MC_SSRCONTROL 46
- 2.10.2 MC_SCRUB_CONTROL 46
- Registers 47
- MC_CHANNEL_1_RANK_TIMING_A 48
- MC_CHANNEL_2_RANK_TIMING_A 48
- MC_CHANNEL_1_REFRESH_TIMING 50
- MC_CHANNEL_2_REFRESH_TIMING 50
- 2.12 Memory Thermal Control 53
- 2.12.5 MC_DDR_THERM1_STATUS0 55
- MC_DDR_THERM1_STATUS1 55
- MC_DDR_THERM1_STATUS2 55
- Register Description 56
- 56 Intel 56
- 3 Functional Description 57
- RAS Modes 61
- 3.5 Memory Error Signaling 62
- 3.7 2X Refresh 63
- Functional Description 64
- 64 Intel 64
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