Intel BXM80536NC1500E Fiche technique Page 8
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8 Intel
®
Celeron
®
M Processor Datasheet
Introduction
The new packed, double-precision, floating-point instructions enhance performance for
applications that require greater range and precision, including scientific and engineering
applications and advanced 3D geometry techniques, such as ray tracing.
The processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The 400-MHz
FSB uses source-synchronous transfer (SST) of address and data to improve performance by
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
“double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning
Transceiver Logic (AGTL+) signal technology, a variant of GTL+ signalling technology with low
power enhancements.
Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other Intel
products.
1.1 Terminology
Term Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address
or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a
hex “A”, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).
FSB
Front Side Bus refers to the interface between the processor and system core logic (also known as
the chipset components).
- Celeron 1
- M Processor 1
- Contents 3
- Revision History 6
- 1 Introduction 7
- 1.1 Terminology 8
- 1.2 References 9
- 1.3 State of Data 9
- Introduction 10
- 2 Low Power Features 11
- 2.1.3 Stop-Grant State 12
- 2.1.4 HALT/Grant Snoop State 12
- 2.1.5 Sleep State 12
- 2.1.6 Deep Sleep State 13
- M Processor Datasheet 14
- 14 Intel 14
- 3 Electrical Specifications 15
- 3.4 Voltage Identification 16
- M Processor Datasheet 17 17
- 3.7 FSB Signal Groups 18
- 3.8 CMOS Signals 19
- 3.9 Maximum Ratings 20
- Electrical Specifications 21
- Static and Ripple Tolerances 22
- Sleep State) 26
- 4 Package Mechanical 29
- 30 Intel 30
- M Processor Datasheet 31 31
- 32 Intel 32
- TOP VIEW BOTTOM VIEW 33
- PACKAGE KEEPOUT 33
- CAPACITOR AREA 33
- 34 Intel 34
- M Processor Datasheet 35 35
- 36 Intel 36
- M Processor Datasheet 37 37
- TOP VIEW 38
- M Processor Datasheet 39 39
- 40 Intel 40
- M Processor Datasheet 41 41
- 42 Intel 42
- M Processor Datasheet 43 43
- 44 Intel 44
- M Processor Datasheet 45 45
- 46 Intel 46
- M Processor Datasheet 47 47
- 48 Intel 48
- M Processor Datasheet 49 49
- 50 Intel 50
- M Processor Datasheet 51 51
- 52 Intel 52
- M Processor Datasheet 53 53
- 54 Intel 54
- M Processor Datasheet 55 55
- 56 Intel 56
- M Processor Datasheet 57 57
- 58 Intel 58
- M Processor Datasheet 59 59
- 60 Intel 60
- M Processor Datasheet 61 61
- 62 Intel 62
- 5 Thermal Specifications and 63
- Celeron M Processor 64
- 5.1 Thermal Specifications 65
- M Processor Datasheet 67 67
- 68 Intel 68
- 6 Debug Tools Specifications 69
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