Intel 8XC196Lx Manuel d'utilisateur Page 41
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Noté. / 5. Basé sur avis des utilisateurs
4-7
STANDARD AND PTS INTERRUPTS
PTSSEL
Address:
Reset State:
0004H
0000H
The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt
service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit
selects a standard interrupt service routine. In PTS modes that use the PTSCOUNT register, hardware
clears the corresponding PTSSEL bit when PTSCOUNT reaches zero. The end-of-PTS interrupt service
routine must reset the PTSSEL bit to re-enable the PTS channel.
15 8
LA
— EXTINT — RI TI SSIO1 SSIO0
—
7 0
— — AD EPA0 EPA1 EPA2 EPA3 EPA
x
15 8
LB
— EXTINT — RI TI SSIO1 SSIO0
J1850ST
7 0
J1850RX J1850TX AD EPA0 EPA1 EPA2 EPA3 EPA
x
15 8
LD
— EXTINT — RI TI SSIO1 SSIO0 —
7 0
— — — EPA0 EPA1 EPA2 EPA3 EPA
x
Bit
Number
Function
14:0
†
Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine.
The PTS interrupt vector locations are as follows:
Bit Mnemonic Interrupt PTS Vector
EXTINT EXTINT pin 205CH
Reserved
†
— 205AH
RI SIO Receive 2058H
TI SIO Transmit 2056H
SSIO1 SSIO 1 Transfer 2054H
SSIO0 SSIO 0 Transfer 2052H
J1850ST (LB) J1850 Status 2050H
J1850RX(LB) J1850 Receive 204EH
J1850TX(LB) J1850 Transmit 204CH
AD(LA, LB) A/D Conversion Complete 204AH
EPA0 EPA Capture/Compare Channel 0 2048H
EPA1 EPA Capture/Compare Channel 1 2046H
EPA2 EPA Capture/Compare Channel 2 2044H
EPA3 EPA Capture/Compare Channel 3 2042H
EPA
x
††
Multiplexed EPA 2040H
††
PTS service is not useful for shared interrupts because the PTS cannot readily
determine the source of these interrupts.
†
Bit 13 is reserved on the 8XC196L
x
devices and bits 6–8 are reserved on the 87C196LA and
83C196LD. For compatibility with future devices, write zeros to these bits.
Figure 4-5. PTS Select (PTSSEL) Register
- 8XC196Lx Supplement to 1
- 8XC196Kx, 8XC196Jx 1
- 87C196CA User’s Manual 1
- Guide to This Manual 9
- CHAPTER 1 11
- GUIDE TO THIS MANUAL 11
- Table 1-1. Related Documents 12
- Architectural 13
- Overview 13
- CHAPTER 2 15
- ARCHITECTURAL OVERVIEW 15
- Figure 2-1. 8XC196L 16
- Block Diagram 16
- Address Space 23
- CHAPTER 3 25
- ADDRESS SPACE 25
- Table 3-3. 8XC196L 28
- Peripheral SFRs 28
- Peripheral SFRs (Continued) 29
- Table 3-4. Windows 30
- Standard and PTS 33
- Interrupts 33
- CHAPTER 4 35
- STANDARD AND PTS INTERRUPTS 35
- 4.2 INTERRUPT REGISTERS 36
- I/O Ports 43
- CHAPTER 5 45
- I/O PORTS 45
- Synchronous Serial 51
- I/O Port 51
- CHAPTER 6 53
- SYNCHRONOUS SERIAL I/O PORT 53
- Address: 54
- Event Processor 57
- CHAPTER 7 59
- EVENT PROCESSOR ARRAY 59
- 7.1.1 EPA Mask Registers 62
- 7.1.2 EPA Pending Registers 63
- Communications 65
- Controller 65
- CHAPTER 8 67
- 8.3.1.2 Bus Contention 71
- 8.3.1.3 Bit Arbitration 71
- 8.3.1.4 Error Detection 71
- A5222-01 73
- 8.4.1.1 Header 75
- 8.4.1.2 CRC Byte 75
- 8.4.1.3 Normalization Bit 75
- A5221-01 77
- . . . . . . . . . 79
- Transmit Byte 80
- Receive Byte 81
- Minimum Hardware 89
- Considerations 89
- CHAPTER 9 91
- Special Operating 93
- CHAPTER 10 95
- SPECIAL OPERATING MODES 95
- Programming the 99
- Nonvolatile Memory 99
- CHAPTER 11 101
- SUPPLEMENT 102
- Table 11-2. 87C196LA, LB 102
- OTPROM Address Map 102
- Signal Descriptions 107
- SIGNAL DESCRIPTIONS 109
- APPENDIX A 109
- Glossary 119
- GLOSSARY 121
- Glossary-2 122
- Glossary-3 123
- Glossary-4 124
- Glossary-5 125
- Glossary-6 126
- Glossary-7 127
- Glossary-8 128
- Glossary-9 129
- Glossary-10 130
- Glossary-11 131
- Glossary-12 132
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