Intel 82555 Manuel d'utilisateur

82555 10/100 Mbps LAN Physical Layer InterfaceNetworking Silicon DatasheetProduct Features Optimal integration for lower cost solutions—Integrated 1

82555 — Networking Silicon6 DatasheetTXERRTransmit Error (repeater mode only)From RIC TXC YesTable 1. 82555 MIISignal NameDescription DirectionClock

Datasheet 7Networking Silicon — 825553.0 Pin DefinitionsAll active digital pins are defined to have transistor-to-transistor logic voltage levels exc

82555 — Networking Silicon8 DatasheetPin allocation is based on a 100-lead quad flat package. All pin locations are based on printed circuit board l

Datasheet 9Networking Silicon — 825553.5 Media Access Control/Repeater Interface Control Pins RXC 90 OReceive Clock. The Receive Clock may be either

82555 — Networking Silicon10 Datasheet3.6 LED Pins 3.7 External Bias Pins Note: The resistor values described for the external bias pins are only re

Datasheet 11Networking Silicon — 825553.8 Miscellaneous Control Pins Symbol Pin Type Name and FunctionRESET 1 IReset. The Reset signal is active high

82555 — Networking Silicon12 Datasheet3.9 Power and Ground Pins Symbol Pin Type Name and FunctionVCC 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 5

Datasheet 13Networking Silicon — 825554.0 100BASE-TX Adapter Mode Operation4.1 100BASE-TX Transmit Clock GenerationA 25 MHz crystal or a 25 MHz oscil

82555 — Networking Silicon14 Datasheet4.2.2 100BASE-TX Scrambler and MLT-3 EncoderData is scrambled in 100BASE-TX in order to reduce electromagnetic

Datasheet 15Networking Silicon — 82555maintained (either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output

82555 — Networking Siliconii DatasheetRevision History Low power consumption—Typical total solution power including all resistors and magnetics:- 275

82555 — Networking Silicon16 Datasheet4.2.4 Transmit DriverThe transmit differential lines are implemented with a digital slope controlled current d

Datasheet 17Networking Silicon — 825554.3.1 Adaptive EqualizerThe distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equ

82555 — Networking Silicon18 Datasheet4.5 100BASE-TX Link Integrity and Auto-Negotiation SolutionThe 82555’s Auto-Negotiation function automatically

Datasheet 19Networking Silicon — 82555The figure below illustrates an 82557/82555/PHY-T4 solution in a block diagram. 4.6 Auto 10/100 Mbps Speed Sele

82555 — Networking Silicon20 Datasheet

Datasheet 21Networking Silicon — 825555.0 10BASE-T Functionality in Adapter Mode5.1 10BASE-T Transmit Clock GenerationThe 20 MHz and 10 MHz clocks ne

82555 — Networking Silicon22 DatasheetTwisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distin

Datasheet 23Networking Silicon — 825555.7 10BASE-T Full DuplexThe 82555 supports 10 Mbps full duplex by disabling the collision function, the squelch

82555 — Networking Silicon24 Datasheet

Datasheet 25Networking Silicon — 825556.0 Repeater ModeThe 82555 has a compete set of repeater features making it the ideal PHY for Class 1 (MII) rep

Datasheet iiiNetworking Silicon — 82555Contents1.0 INTRODUCTION...

82555 — Networking Silicon26 DatasheetPHYs connected to the RIC. Signals TXEN, CRS, and PORTEN are connected from each of the 82555 devices to the s

Datasheet 27Networking Silicon — 825557.0 Management Data InterfaceThe 82555 provides status and accepts management information through the Managemen

82555 — Networking Silicon28 DatasheetThe 82555 address can be configured to four 0 through 3 in DTE (adapter) mode and 0 through 31 in repeater mod

Datasheet 29Networking Silicon — 825557.2.1.2 Register 1: Status Register Bit Definitions 11 Power-Down This bit sets the 82555 into a low power mode

82555 — Networking Silicon30 Datasheet7.2.1.3 Register 2: 82555 Identifier Register Bit Definitions 7.2.1.4 Register 3: 82555 Identifier Register Bi

Datasheet 31Networking Silicon — 825557.2.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions 7.2.1.7 Register 6: Auto-Neg

82555 — Networking Silicon32 Datasheet7.2.3.1 Register 16: 82555 Status and Control Register Bit Definitions 7.2.3.2 Register 17: 82555 Special Cont

Datasheet 33Networking Silicon — 825557.2.3.3 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions 7.2.3.4 Register 21: 100BASE-TX Rece

82555 — Networking Silicon34 Datasheet7.2.3.5 Register 22: Receive Symbol Error Counter Bit Definitions 7.2.3.6 Register 23: 100BASE-TX Receive Prem

Datasheet 35Networking Silicon — 825558.0 Auto-Negotiation FunctionalityThe 82555 supports Auto-Negotiation. Auto-Negotiation is a scheme of auto-con

82555 — Networking Siliconiv DatasheetContents5.3.3 10BASE-T Error Detection and Reporting ...225.4 10

82555 — Networking Silicon36 DatasheetTo detect the correct technology, the two register fields should be ANDed together to obtain the highest commo

Datasheet 37Networking Silicon — 82555Negotiation or Parallel Detection with no data packets being transmitted. Connection is then established either

82555 — Networking Silicon38 Datasheet

Datasheet 39Networking Silicon — 825559.0 LED DescriptionsThe 82555 supports four LED pins to indicate link status, network activity and network spee

82555 — Networking Silicon40 Datasheet

Datasheet 41Networking Silicon — 8255510.0 Reset and Miscellaneous Test Modes10.1 ResetWhen the 82555 RESET signal is asserted (high), all internal c

82555 — Networking Silicon42 DatasheetThe TOUT pin is controlled by different sources according to the active test instruction. The TOUT signal is a

Datasheet 43Networking Silicon — 8255511.0 Electrical Specifications and Timing Parameters11.1 Absolute Maximum Ratings 11.2 General Operating Condit

82555 — Networking Silicon44 Datasheet11.3.3 100BASE-TX Voltage/Current DC Characteristics VIDA10Input differential accept voltage5 MHz ≤ f ≤ 10 MHz

Datasheet 45Networking Silicon — 8255511.4 AC Characteristics11.4.1 MII Clock SpecificationsICC100cCurrent on all VCC pins 235 mAICCT100TOTTotal supp

Datasheet 1Networking Silicon — 825551.0 IntroductionThe 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 Mbps

82555 — Networking Silicon46 Datasheet11.4.2 MII Timing Parameters Figure 14. MII Clocks AC TimingT1,T2,T31.5VT4,T5,T6T4,T5,T6Symbol Parameter Condi

Datasheet 47Networking Silicon — 8255511.4.3 Repeater Mode Timing Parameters Figure 16. MII Receive Timing ParametersFigure 17. MII Timing Parameters

82555 — Networking Silicon48 Datasheet11.4.4 Transmit Packet Timing Parameters 11.4.5 Squelch Test Timing Parameters Symbol Parameter Conditions Min

Datasheet 49Networking Silicon — 8255511.4.6 Jabber Timing Parameters 11.4.7 Receive Packet Timing Parameters Figure 20. Squelch Test Timing Paramete

82555 — Networking Silicon50 Datasheet11.4.8 10BASE-T Normal Link Pulse (NLP) Timing Parameters 11.4.9 Auto-Negotiation Fast Link Pulse (FLP) Timing

Datasheet 51Networking Silicon — 8255511.4.10 Reset Timing Parameters 11.4.11 X1 Clock Specifications T33 TFLP_BUR_NUMNumber of pulses in one burst 1

82555 — Networking Silicon52 Datasheet11.4.12 100BASE-TX Transmitter AC Specification Figure 26. X1 Clock SpecificationsT382.5VT39T390.4V4.0VSymbol

Datasheet 53Networking Silicon — 8255512.0 82555 Package InformationThis section provides the physical packaging information for the 82555. The 82555

82555 — Networking Silicon54 DatasheetT Lead Angle 0.0 - 10.0Y Coplanarity - - 0.10Table 7. Dimensions for the 82555 QFPSymbol Description Min Norm

82555 — Networking Silicon2 DatasheetThe 82555 also complies with the IEEE 802.3u Auto-Negotiation and the IEEE 802.3x Full Duplex Flow Control sect

Datasheet 3Networking Silicon — 825552.0 Architectural OverviewThe 82555 is an advanced combination of both digital and analog logic which combine to

82555 — Networking Silicon4 Datasheet•Receive: The 82555 takes receive analog MLT-3 data from the receive differential pair and converts it into a d

Datasheet 5Networking Silicon — 82555The 82555 provides a glueless interface to Intel components such as the 82557 Fast Ethernet Controller, as well