Intel Core 2 Duo E7300 Spécifications

Intel® Core™2 Duo Processor E8000Δ and E7000Δ Series Specification Update — on 45 nm Process in the 775-land LGA Package June 2009

Summary Tables of Changes 10 Intel® Core™2 Duo Processor Specification Update AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo pro

Summary Tables of Changes Intel® Core™2 Duo Processor Specification Update 11 NO C0 M0 E0 R0 Plan ERRATA AW4 X X X X No Fix Non-Temporal Data

Summary Tables of Changes 12 Intel® Core™2 Duo Processor Specification Update NO C0 M0 E0 R0 Plan ERRATA AW25 X X X X No Fix Writing the Loc

Summary Tables of Changes Intel® Core™2 Duo Processor Specification Update 13 NO C0 M0 E0 R0 Plan ERRATA AW45 X X Fixed Partial Streami

Summary Tables of Changes 14 Intel® Core™2 Duo Processor Specification Update NO C0 M0 E0 R0 Plan ERRATA AW67 X X No Fix Enabling PECI v

Identification Information Intel® Core™2 Duo Processor Specification Update 15 Identification Information Figure 1. Processor Package Example

Component Identification Information 16 Intel® Core™2 Duo Processor Specification Update Component Identification Information The Intel® Core™2

Component Identification Information Intel® Core™2 Duo Processor Specification Update 17 Table 1. Intel® Core™2 Duo Processor Identification In

Errata 18 Intel® Core™2 Duo Processor Specification Update Errata AW1. EFLAGS Discrepancy on Page Faults after a Translation Change Problem: T

Errata Intel® Core™2 Duo Processor Specification Update 19 AW3. Store to WT Memory Data May be Seen in Wrong Order by Two Subsequent Loads Prob

2 Intel® Core™2 Duo Processor Specification Update INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO

Errata 20 Intel® Core™2 Duo Processor Specification Update Violation #GP (General Protection Fault). Due to this erratum, code #PF may be handl

Errata Intel® Core™2 Duo Processor Specification Update 21 Workaround: None identified. Status: For the steppings affected, see the Summary Tabl

Errata 22 Intel® Core™2 Duo Processor Specification Update AW12. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check Problem: C

Errata Intel® Core™2 Duo Processor Specification Update 23 AW15. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundarie

Errata 24 Intel® Core™2 Duo Processor Specification Update Workaround: None identified. Status: For the steppings affected, see the Summary Tab

Errata Intel® Core™2 Duo Processor Specification Update 25 AW21. Premature Execution of a Load Operation Prior to Exception Handler Invocation

Errata 26 Intel® Core™2 Duo Processor Specification Update b) RSM from an SMI during a HLT instruction. Implication: There may be a smaller t

Errata Intel® Core™2 Duo Processor Specification Update 27 will be left set in the in-service register and mask all interrupts at the same or low

Errata 28 Intel® Core™2 Duo Processor Specification Update  The processor is in protected mode with paging enabled and the page global enable

Errata Intel® Core™2 Duo Processor Specification Update 29 Problem: Software which is written so that multiple agents can modify the same shared

Intel® Core™2 Duo Processor Specification Update 3

Errata 30 Intel® Core™2 Duo Processor Specification Update Problem: CPUID leaf 0Ah reports the architectural performance monitoring version tha

Errata Intel® Core™2 Duo Processor Specification Update 31 Workaround: BIOS must leave the xTPR update transactions disabled (default). Status:

Errata 32 Intel® Core™2 Duo Processor Specification Update Implication: This erratum has not been observed with commercially available software

Errata Intel® Core™2 Duo Processor Specification Update 33 VM-execution control field above that of the TPR shadow while either of those bits is

Errata 34 Intel® Core™2 Duo Processor Specification Update should (1) save from the VMCS (using VMREAD) the value of RIP before any VM entry to

Errata Intel® Core™2 Duo Processor Specification Update 35 Problem: If instructions from at least three different ways in the same instruction c

Errata 36 Intel® Core™2 Duo Processor Specification Update Problem: RSM instruction execution, under certain conditions triggered by a complex

Errata Intel® Core™2 Duo Processor Specification Update 37 [r/e]BP instructions without having an invalid stack during interrupt handling. Howeve

Errata 38 Intel® Core™2 Duo Processor Specification Update Implication: IA32_MC1_STATUS MSR bit [60] may not reflect the correct state of the e

Errata Intel® Core™2 Duo Processor Specification Update 39 Status: For the steppings affected, see the Summary Tables of Changes. AW57. IRET un

4 Intel® Core™2 Duo Processor Specification Update Contents Contents ...

Errata 40 Intel® Core™2 Duo Processor Specification Update Implication: In the event of a thermal event while a processor is waking up from Int

Errata Intel® Core™2 Duo Processor Specification Update 41 the PECI hold-off indication by keeping the PECI bus high when the PECI host sends the

Errata 42 Intel® Core™2 Duo Processor Specification Update AW65. Global Instruction TLB Entries May Not be Invalidated on a VM Exit or VM Entry

Errata Intel® Core™2 Duo Processor Specification Update 43 AW68. INIT Incorrectly Resets IA32_LSTAR MSR Problem: In response to an INIT reset i

Errata 44 Intel® Core™2 Duo Processor Specification Update Workaround: None identified. Status: For the steppings affected, see the Summary Tab

Errata Intel® Core™2 Duo Processor Specification Update 45 Implication: Execution of the stores in XSAVE, when XSAVE is used to store SSE contex

Errata 46 Intel® Core™2 Duo Processor Specification Update AW76. A Page Fault May Not be Generated When the PS bit is set to “1” in a PML4E or

Specification Changes Intel® Core™2 Duo Processor Specification Update 47 Specification Changes The Specification Changes listed in this section

Specification Clarifications 48 Intel® Core™2 Duo Processor Specification Update Specification Clarifications The Specification Clarifications l

Documentation Changes Intel® Core™2 Duo Processor Specification Update 49 Documentation Changes The Documentation Changes listed in this section

Intel® Core™2 Duo Processor Specification Update 5 Revision History Revision Number Description Date 001 Initial release of Intel® Core™2 Duo

Preface 6 Intel® Core™2 Duo Processor Specification Update Preface This document is an update to the specifications contained in the documents l

Preface Intel® Core™2 Duo Processor Specification Update 7 Nomenclature S-Spec Number is a five-digit code used to identify products. Products ar

Summary Tables of Changes 8 Intel® Core™2 Duo Processor Specification Update Summary Tables of Changes The following table indicates the Specifi

Summary Tables of Changes Intel® Core™2 Duo Processor Specification Update 9 Item Numbering Each Specification Update item is prefixed with a ca