Intel SC5299UPNA Fiche technique télécharger pdf (Page 119)

Power Sub-system Intel

Entry Server Chassis SC5299-E TPS

Revision 3.1

Intel order number D37594-005

104

2.5.10.2 PWOK (Power OK) Output Signal

PWOK is a power OK signal and is pulled HIGH by the power supply to indicate that all the

outputs are within the regulation limits of the power supply. When any output voltage falls below

regulation limits or when AC power has been removed for a time sufficiently long so that power

supply operation is no longer guaranteed, PWOK will be de-asserted to a LOW state. The start

of the PWOK delay time is inhibited as long as any power supply output is in current limit.

Table 128. PWOK Signal Characteristics

Signal Type

Open collector/drain output from power supply. Pull-up

to VSB located in system.

PWOK = High Power OK

PWOK = Low Power Not OK

MIN MAX

Logic level low voltage, Isink=4mA 0V 0.4V

Logic level high voltage, Isource=200 A

2.4V 5.25V

Sink current, PWOK = low 4mA

Source current, PWOK = high 2mA

PWOK delay: T

pwok_on

100ms 1000ms

PWOK rise and fall time

100 sec

Power down delay: T

pwok_off

1ms 200msec

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Intel SC5299UPNA Fiche technique Page 119