Intel NETWORK PROCESSOR IXP2800 manuels

Manuels d'utilisation et guides de l'utilisateur pour Ordinateurs Intel NETWORK PROCESSOR IXP2800.
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Intel NETWORK PROCESSOR IXP2800 Manuel d'utilisateur (430 pages)

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Table des matières

IXP2800 Network

1

Processor

1

Revision History

2

Contents

24

Introduction 1

25

1.3 Terminology

26

Technical Description 2

27

IXP2800 Network Processor

28

Technical Description

28

2.2 Intel XScale

30

Core Microarchitecture

30

2.2.2.4 Branch Target Buffer

31

2.2.2.5 Data Cache

31

2.2.2.6 Interrupt Controller

31

2.2.2.7 Address Map

32

2.3 Microengines

33

2.3.2 Control Store

35

2.3.3 Contexts

35

2.3.4 Datapath Registers

37

38 Hardware Reference Manual

38

2.3.4.4 Local Memory

39

40 Hardware Reference Manual

40

2.3.5 Addressing Modes

41

42 Hardware Reference Manual

42

2.3.6 Local CSRs

43

2.3.7 Execution Datapath

43

44 Hardware Reference Manual

44

2.3.7.2 CAM

45

46 Hardware Reference Manual

46

2.3.8 CRC Unit

48

2.3.9 Event Signals

49

2.4 DRAM

50

2.5 SRAM

51

52 Hardware Reference Manual

52

2.5.3 SRAM Atomic Operations

53

2.5.5 Reference Ordering

54

Hardware Reference Manual 55

55

2.6 Scratchpad Memory

56

Scratchpad RAM

57

58 Hardware Reference Manual

58

Hardware Reference Manual 59

59

2.7.1 SPI-4

60

2.7.2 CSIX

61

2.7.3 Receive

61

2.7.3.1 RBUF

62

2.7.3.2 Full Element List

63

2.7.3.3 RX_THREAD_FREELIST

63

64 Hardware Reference Manual

64

2.7.4 Transmit

65

66 Hardware Reference Manual

66

Hardware Reference Manual 67

67

2.7.5.1 SPI-4

68

2.7.5.2 CSIX

68

2.8 Hash Unit

69

2.9 PCI Controller

71

2.9.3.1 DMA Descriptor

72

2.9.3.2 DMA Channel Operation

73

74 Hardware Reference Manual

74

2.9.5 PCI Arbiter

75

2.11 Intel XScale

76

Core Peripherals

76

2.11.2 Timers

77

2.11.3 General Purpose I/O

77

2.11.5 Slowport

77

2.12 I/O Latency

78

2.13 Performance Monitor

78

3.2 Features

80

Hardware Reference Manual 81

81

3.3 Memory Management

82

Hardware Reference Manual 83

83

3.3.2 Exceptions

84

3.3.4 Control

85

3.3.4.3 Locking Entries

86

Hardware Reference Manual 87

87

3.4 Instruction Cache

88

Hardware Reference Manual 89

89

3.4.1.3 Fetch Policy

90

3.4.1.5 Parity Protection

91

3.4.2.2 Enabling/Disabling

92

Hardware Reference Manual 93

93

94 Hardware Reference Manual

94

SN WN WT ST

95

3.6 Data Cache

96

3.6.1 Overviews

97

98 Hardware Reference Manual

98

Hardware Reference Manual 99

99

3.6.2.3 Cache Policies

100

• The MMU is enabled

100

Hardware Reference Manual 101

101

3.6.2.5 Parity Protection

102

3.6.2.6 Atomic Accesses

102

3.6.3.2 Enabling/Disabling

103

104 Hardware Reference Manual

104

Hardware Reference Manual 105

105

3.7 Configuration

106

3.8 Performance Monitoring

107

108 Hardware Reference Manual

108

Hardware Reference Manual 109

109

110 Hardware Reference Manual

110

Hardware Reference Manual 111

111

3.9.1 Interrupt Latency

112

3.9.2 Branch Prediction

112

3.9.3 Addressing Modes

113

3.9.4 Instruction Latencies

113

• Minimum Resource Latency

114

Hardware Reference Manual 115

115

IXP2800 Network Processor

116

Intel XScale

116

Hardware Reference Manual 117

117

118 Hardware Reference Manual

118

3.10 Test Features

119

• SRAM and DRAM access:

120

• PCI Accesses

120

Hardware Reference Manual 121

121

IXP2800

122

Core Gasket

122

• Byte Write

123

• Word Write (16 bits)

123

• Longword write (32 bits)

123

Byte Write by Intel XScale

124

3.11 Intel XScale

125

Core Gasket Unit

125

Word 0Word 1

125

3.11.4 Atomic Operations

128

Hardware Reference Manual 129

129

3.11.5 I/O Transaction

130

3.11.6 Hash Access

130

3.11.7 Gasket Local CSR

131

3.11.8 Interrupt

132

3.12 Intel XScale

134

Core Peripheral Interface

134

3.12.1.1 Data Transfers

135

3.12.1.2 Data Alignment

135

136 Hardware Reference Manual

136

3.12.2 UART Overview

137

B1741-02

138

3.12.4 Baud Rate Generator

139

140 Hardware Reference Manual

140

3.12.6 Timers

141

3.12.7 Slowport Unit

142

3.12.7.1 PROM Device Support

143

144 Hardware Reference Manual

144

3FFFFFFh

145

23FFFFFh

145

2000000h

145

03FFFFFh

145

0000000h

145

17:10 24:189:2 17:10 24:189:2

147

24:1817:109:2 24:1817:109:2

148

Hardware Reference Manual 149

149

D[7:0] D[7:0]

150

Hardware Reference Manual 151

151

Hardware Reference Manual 153

153

154 Hardware Reference Manual

154

Hardware Reference Manual 155

155

156 Hardware Reference Manual

156

Hardware Reference Manual 157

157

158 Hardware Reference Manual

158

160 Hardware Reference Manual

160

Hardware Reference Manual 161

161

162 Hardware Reference Manual

162

164 Hardware Reference Manual

164

Hardware Reference Manual 165

165

Microengines 4

167

Microengines

168

4.1.1 Control Store

169

4.1.2 Contexts

169

Inactive Ready

170

Sleep Executing

170

4.1.3 Datapath Registers

171

4.1.3.4 Local Memory

172

4.1.4 Addressing Modes

173

4.2 Local CSRs

174

4.3 Execution Datapath

174

Hardware Reference Manual 175

175

4.3.2 CAM

176

Hardware Reference Manual 177

177

4.4 CRC Unit

179

4.5 Event Signals

180

4.5.1 Microengine Endianness

181

4.5.1.2 Write to TBUF

182

4.5.2 Media Access

183

4.5.2.1 Read from RBUF

184

4.5.2.2 Write to TBUF

185

186 Hardware Reference Manual

186

5.1 Overview

187

5.2 Size Configuration

188

5.3 DRAM Clocking

189

5.4 Bank Policy

190

5.5 Interleaving

191

Hardware Reference Manual 193

193

5.6 Parity and ECC

194

5.6.2 Parity Enabled

195

5.6.3 ECC Enabled

195

5.7 Timing Configuration

196

5.8 Microengine Signals

197

5.9 Serial Port

197

198 Hardware Reference Manual

198

5.10.1 Commands

199

5.10.2 DRAM Write

199

5.10.3 DRAM Read

200

5.10.4 CSR Write

200

5.10.5 CSR Read

200

5.11 DRAM Push/Pull Arbiter

201

202 Hardware Reference Manual

202

Hardware Reference Manual 203

203

204 Hardware Reference Manual

204

Hardware Reference Manual 205

205

SRAM Interface 6

207

208 Hardware Reference Manual

208

6.2.1 Internal Interface

209

6.2.2 Number of Channels

209

210 Hardware Reference Manual

210

6.4 Command Overview

211

212 Hardware Reference Manual

212

A9736-01

213

A9737-01

213

A9739-01

214

6.5 Parity

217

6.6 Address Map

218

6.7 Reference Ordering

219

220 Hardware Reference Manual

220

6.8 Coprocessor Mode

221

Network Processor

222

Coprocessor

222

Hardware Reference Manual 223

223

SRAM Interface

224

SHaC — Unit Expansion 7

225

SHaC — Unit Expansion

226

7.1.2 Scratchpad

227

7.1.2.2 Scratchpad Interface

229

230 Hardware Reference Manual

230

A9757-01

231

232 Hardware Reference Manual

232

Hardware Reference Manual 233

233

Signal Done

234

Hardware Reference Manual 235

235

7.1.3 Hash Unit

236

7.1.3.1 Hashing Operation

237

238 Hardware Reference Manual

238

7.1.3.2 Hash Algorithm

239

8.1 Overview

241

242 Hardware Reference Manual

242

8.1.1 SPI-4

243

244 Hardware Reference Manual

244

Hardware Reference Manual 245

245

8.1.2 CSIX

246

8.2 Receive

247

8.2.1 Receive Pins

248

8.2.2 RBUF

248

Hardware Reference Manual 249

249

8.2.2.1 SPI-4

250

. The temporary

251

252 Hardware Reference Manual

252

8.2.2.2 CSIX

253

• Place into FCEFIFO

253

254 Hardware Reference Manual

254

8.2.3 Full Element List

255

8.2.4 Rx_Thread_Freelist_#

255

256 Hardware Reference Manual

256

Hardware Reference Manual 257

257

8.2.7.1 SPI-4

258

• The RBUF upper limit

258

• RX_PORT_CALENDAR_STATUS_#

258

Hardware Reference Manual 259

259

8.2.8 Parity

260

8.2.9 Error Cases

261

8.3 Transmit

262

8.3.2 TBUF

263

Hardware Reference Manual 265

265

8.3.2.1 SPI-4

266

8.3.2.2 CSIX

267

8.3.3.1 SPI-4

268

8.3.3.2 CSIX

269

8.3.3.3 Transmit Summary

270

8.3.4.1 SPI-4

271

272 Hardware Reference Manual

272

8.3.5 Parity

273

8.4 RBUF and TBUF Summary

274

Hardware Reference Manual 275

275

276 Hardware Reference Manual

276

8.5.2.1 Full Duplex CSIX

277

8.5.2.2 Simplex CSIX

278

Hardware Reference Manual 279

279

8.6 Deskew and Training

280

Hardware Reference Manual 281

281

8.6.1 Data Training Pattern

282

8.6.3 Use of Dynamic Training

283

284 Hardware Reference Manual

284

Hardware Reference Manual 285

285

286 Hardware Reference Manual

286

8.7 CSIX Startup Sequence

287

8.7.2 CSIX Simplex

288

Hardware Reference Manual 289

289

290 Hardware Reference Manual

290

Hardware Reference Manual 291

291

B2735-01

293

SPI-4.2 LVTTL Reverse Path

294

DDR LVDS Flow Control

294

SPI-4.2 Forward Path

294

Serial CSIX

295

Ready Bits

295

Flow Control

295

CSIX Flow Control CFramers

295

(Provides multiple interfaces

296

Full Duplex

296

Interface

296

(SPI-4.2 and CSIX-L1)

297

B2745-01

298

B2747-01

299

Fabric Interface Chip

300

8.9.3.1 SPI-4.2 Receiver

301

8.9.3.2 SPI-4.2 Transmitter

302

Interface Chip

303

8.9.4.2 Intel

304

• A clock (TXCCLK, RXCCLK)

305

Support for Simplex Operation

306

Hardware Reference Manual 307

307

308 Hardware Reference Manual

308

Hardware Reference Manual 309

309

310 Hardware Reference Manual

310

Hardware Reference Manual 311

311

312 Hardware Reference Manual

312

Hardware Reference Manual 313

313

8.9.6 Transmit State Machine

314

Hardware Reference Manual 315

315

8.9.7 Dynamic De-Skew

316

PCI Unit 9

319

PCI Unit

320

Hardware Reference Manual 321

321

9.2.1 PCI Commands

322

Hardware Reference Manual 323

323

324 Hardware Reference Manual

324

• The PCI_AD [1:0] are 00

325

9.2.3.1 Configuration Write

325

9.2.3.2 Configuration Read

325

9.2.5 PCI Target Cycles

326

Hardware Reference Manual 327

327

328 Hardware Reference Manual

328

9.2.8 PCI Retry

329

9.2.9 PCI Disconnect

329

9.2.11 PCI Central Functions

330

PCI Master

331

State Machine

331

PCI Arbiter

331

PCI UNIT

331

9.3 Slave Interface Block

332

9.3.2 SRAM Interface

333

9.3.3 DRAM Interface

334

9.3.3.2 DRAM Slave Reads

335

336 Hardware Reference Manual

336

Hardware Reference Manual 337

337

338 Hardware Reference Manual

338

9.3.5 PCI Interrupt Pin

339

9.4 Master Interface Block

340

Hardware Reference Manual 341

341

9.4.1.3 DMA Descriptor

342

9.4.1.4 DMA Channel Operation

343

344 Hardware Reference Manual

344

9.4.1.8 PCI to DRAM Transfer

345

Status Registers

346

A9776-02

347

9.5 PCI Unit Error Behavior

348

Hardware Reference Manual 349

349

350 Hardware Reference Manual

350

Core or Microengine

351

352 Hardware Reference Manual

352

Hardware Reference Manual 353

353

354 Hardware Reference Manual

354

9.6.1 Endian for Byte Enable

355

356 Hardware Reference Manual

356

Hardware Reference Manual 357

357

Stepping Description

358

Clocks and Reset 10

359

Clocks and Reset

360

Hardware Reference Manual 361

361

362 Hardware Reference Manual

362

Hardware Reference Manual 363

363

10.3 Reset

364

Hardware Reference Manual 365

365

10.3.2 PCI-Initiated Reset

366

Hardware Reference Manual 367

367

10.3.6 Strap Pins

368

10.4 Boot Mode

370

Figure 135. Boot Process

371

10.4.1 Flash ROM

372

10.4.2 PCI Host Download

372

10.5 Initialization

373

Performance Monitor Unit 11

375

Performance Monitoring

376

Hardware Reference Manual 377

377

378 Hardware Reference Manual

378

Performance Monitor Unit

379

380 Hardware Reference Manual

380

11.2.1 APB Peripheral

381

11.2.2 CAP Description

381

11.3 Performance Measurements

382

11.4.2 Count Events

385

386 Hardware Reference Manual

386

11.4.4 Null Event

387

11.4.5 Threshold Events

388

11.4.6 External Input Events

389

Design Block #(0110)

396

11.4.6.4 Intel XScale

402

Design Block #(0111)

402

Table 158. Intel XScale

403

Hardware Reference Manual 405

405

Design Block #(0011)

425

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